Commit b45d322c authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add CPU and cache topology for Tegra194 



Tegra194 has four CPU clusters, each with their own cache hierarchy.
This patch creates the CPU map for these clusters and adds the second-
and third-level caches and associates them with the CPUs.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d440538e

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+144 −12
Original line number Diff line number Diff line
@@ -1478,60 +1478,192 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

		cpu0_0: cpu@0 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10000>;

			reg = <0x000>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_0>;

		};



		cpu@1 {

		cpu0_1: cpu@1 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10001>;

			reg = <0x001>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_0>;

		};



		cpu@2 {

		cpu1_0: cpu@100 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x100>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_1>;

		};



		cpu@3 {

		cpu1_1: cpu@101 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x101>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_1>;

		};



		cpu@4 {

		cpu2_0: cpu@200 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x200>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_2>;

		};



		cpu@5 {

		cpu2_1: cpu@201 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x201>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_2>;

		};



		cpu@6 {

		cpu3_0: cpu@300 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10300>;

			reg = <0x300>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_3>;

		};



		cpu@7 {

		cpu3_1: cpu@301 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10301>;

			reg = <0x301>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_3>;

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu0_0>;

				};



				core1 {

					cpu = <&cpu0_1>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&cpu1_0>;

				};



				core1 {

					cpu = <&cpu1_1>;

				};

			};



			cluster2 {

				core0 {

					cpu = <&cpu2_0>;

				};



				core1 {

					cpu = <&cpu2_1>;

				};

			};



			cluster3 {

				core0 {

					cpu = <&cpu3_0>;

				};



				core1 {

					cpu = <&cpu3_1>;

				};

			};

		};



		l2c_0: l2-cache0 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l2c_1: l2-cache1 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l2c_2: l2-cache2 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l2c_3: l2-cache3 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l3c: l3-cache {

			cache-size = <4194304>;

			cache-line-size = <64>;

			cache-sets = <4096>;

		};

	};

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