Commit b3b4f8df authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Geert Uytterhoeven
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pinctrl: sh-pfc: r8a77980: Add RPC pins, groups, and functions 



Add the RPC pins/groups/functions to the R8A77980 PFC driver.
They can be used if an Octal-SPI flash or HyperFlash is connected.

Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/fd089d37-95bb-4ec9-282f-e04d7e5195e4@cogentembedded.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b3a9e3b9

drivers/pinctrl/sh-pfc/pfc-r8a77980.c

+76 −0
Original line number Diff line number Diff line
@@ -1710,6 +1710,64 @@ static const unsigned int qspi1_data4_mux[] = { 
	QSPI1_IO2_MARK, QSPI1_IO3_MARK

};



/* - RPC -------------------------------------------------------------------- */

static const unsigned int rpc_clk1_pins[] = {

	/* Octal-SPI flash: C/SCLK */

	RCAR_GP_PIN(5, 0),

};

static const unsigned int rpc_clk1_mux[] = {

	QSPI0_SPCLK_MARK,

};

static const unsigned int rpc_clk2_pins[] = {

	/* HyperFlash: CK, CK# */

	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),

};

static const unsigned int rpc_clk2_mux[] = {

	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,

};

static const unsigned int rpc_ctrl_pins[] = {

	/* Octal-SPI flash: S#/CS, DQS */

	/* HyperFlash: CS#, RDS */

	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),

};

static const unsigned int rpc_ctrl_mux[] = {

	QSPI0_SSL_MARK, QSPI1_SSL_MARK,

};

static const unsigned int rpc_data_pins[] = {

	/* DQ[0:7] */

	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),

	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),

	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),

	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),

};

static const unsigned int rpc_data_mux[] = {

	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,

	QSPI0_IO2_MARK, QSPI0_IO3_MARK,

	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,

	QSPI1_IO2_MARK, QSPI1_IO3_MARK,

};

static const unsigned int rpc_reset_pins[] = {

	/* RPC_RESET# */

	RCAR_GP_PIN(5, 12),

};

static const unsigned int rpc_reset_mux[] = {

	RPC_RESET_N_MARK,

};

static const unsigned int rpc_int_pins[] = {

	/* RPC_INT# */

	RCAR_GP_PIN(5, 14),

};

static const unsigned int rpc_int_mux[] = {

	RPC_INT_N_MARK,

};

static const unsigned int rpc_wp_pins[] = {

	/* RPC_WP# */

	RCAR_GP_PIN(5, 13),

};

static const unsigned int rpc_wp_mux[] = {

	RPC_WP_N_MARK,

};



/* - SCIF0 ------------------------------------------------------------------ */

static const unsigned int scif0_data_pins[] = {

	/* RX0, TX0 */
@@ -2126,6 +2184,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(qspi1_ctrl),

	SH_PFC_PIN_GROUP(qspi1_data2),

	SH_PFC_PIN_GROUP(qspi1_data4),

	SH_PFC_PIN_GROUP(rpc_clk1),

	SH_PFC_PIN_GROUP(rpc_clk2),

	SH_PFC_PIN_GROUP(rpc_ctrl),

	SH_PFC_PIN_GROUP(rpc_data),

	SH_PFC_PIN_GROUP(rpc_reset),

	SH_PFC_PIN_GROUP(rpc_int),

	SH_PFC_PIN_GROUP(rpc_wp),

	SH_PFC_PIN_GROUP(scif0_data),

	SH_PFC_PIN_GROUP(scif0_clk),

	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2362,6 +2427,16 @@ static const char * const qspi1_groups[] = { 
	"qspi1_data4",

};



static const char * const rpc_groups[] = {

	"rpc_clk1",

	"rpc_clk2",

	"rpc_ctrl",

	"rpc_data",

	"rpc_reset",

	"rpc_int",

	"rpc_wp",

};



static const char * const scif0_groups[] = {

	"scif0_data",

	"scif0_clk",
@@ -2460,6 +2535,7 @@ static const struct sh_pfc_function pinmux_functions[] = { 
	SH_PFC_FUNCTION(pwm4),

	SH_PFC_FUNCTION(qspi0),

	SH_PFC_FUNCTION(qspi1),

	SH_PFC_FUNCTION(rpc),

	SH_PFC_FUNCTION(scif0),

	SH_PFC_FUNCTION(scif1),

	SH_PFC_FUNCTION(scif3),

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