Commit b3b03052 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: refine powerplay code. 



delete struct smumgr, put smu backend function table
in struct hwmgr

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 221c89f9

drivers/gpu/drm/amd/powerplay/amd_powerplay.c

+25 −37
Original line number Diff line number Diff line
@@ -35,13 +35,13 @@ static inline int pp_check(struct pp_instance *handle) 
	if (handle == NULL || handle->pp_valid != PP_VALID)

		return -EINVAL;



	if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL)

	if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)

		return -EINVAL;



	if (handle->pm_en == 0)

		return PP_DPM_DISABLED;



	if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL)

	if (handle->hwmgr->hwmgr_func == NULL)

		return PP_DPM_DISABLED;



	return 0;
@@ -52,38 +52,32 @@ static int pp_early_init(void *handle) 
	int ret;

	struct pp_instance *pp_handle = (struct pp_instance *)handle;



	ret = smum_early_init(pp_handle);

	ret = hwmgr_early_init(pp_handle);

	if (ret)

		return ret;

		return -EINVAL;



	if ((pp_handle->pm_en == 0)

		|| cgs_is_virtualization_enabled(pp_handle->device))

		return PP_DPM_DISABLED;



	ret = hwmgr_early_init(pp_handle);

	if (ret) {

		pp_handle->pm_en = 0;

		return PP_DPM_DISABLED;

	}



	return 0;

}



static int pp_sw_init(void *handle)

{

	struct pp_smumgr *smumgr;

	struct pp_hwmgr *hwmgr;

	int ret = 0;

	struct pp_instance *pp_handle = (struct pp_instance *)handle;



	ret = pp_check(pp_handle);



	if (ret == 0 || ret == PP_DPM_DISABLED) {

		smumgr = pp_handle->smu_mgr;

		hwmgr = pp_handle->hwmgr;



		if (smumgr->smumgr_funcs->smu_init == NULL)

		if (hwmgr->smumgr_funcs->smu_init == NULL)

			return -EINVAL;



		ret = smumgr->smumgr_funcs->smu_init(pp_handle->hwmgr);

		ret = hwmgr->smumgr_funcs->smu_init(hwmgr);



		pr_info("amdgpu: powerplay sw initialized\n");

	}
@@ -92,39 +86,39 @@ static int pp_sw_init(void *handle) 


static int pp_sw_fini(void *handle)

{

	struct pp_smumgr *smumgr;

	struct pp_hwmgr *hwmgr;

	int ret = 0;

	struct pp_instance *pp_handle = (struct pp_instance *)handle;



	ret = pp_check(pp_handle);

	if (ret == 0 || ret == PP_DPM_DISABLED) {

		smumgr = pp_handle->smu_mgr;

		hwmgr = pp_handle->hwmgr;



		if (smumgr->smumgr_funcs->smu_fini == NULL)

		if (hwmgr->smumgr_funcs->smu_fini == NULL)

			return -EINVAL;



		ret = smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);

		ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);

	}

	return ret;

}



static int pp_hw_init(void *handle)

{

	struct pp_smumgr *smumgr;

	int ret = 0;

	struct pp_instance *pp_handle = (struct pp_instance *)handle;

	struct pp_hwmgr *hwmgr;



	ret = pp_check(pp_handle);



	if (ret == 0 || ret == PP_DPM_DISABLED) {

		smumgr = pp_handle->smu_mgr;

		hwmgr = pp_handle->hwmgr;



		if (smumgr->smumgr_funcs->start_smu == NULL)

		if (hwmgr->smumgr_funcs->start_smu == NULL)

			return -EINVAL;



		if(smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {

		if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {

			pr_err("smc start failed\n");

			smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);

			hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);

			return -EINVAL;;

		}

		if (ret == PP_DPM_DISABLED)
@@ -137,8 +131,6 @@ static int pp_hw_init(void *handle) 
	return 0;

err:

	pp_handle->pm_en = 0;

	kfree(pp_handle->hwmgr);

	pp_handle->hwmgr = NULL;

	return PP_DPM_DISABLED;

}
@@ -232,7 +224,7 @@ static int pp_suspend(void *handle) 


static int pp_resume(void *handle)

{

	struct pp_smumgr *smumgr;

	struct pp_hwmgr  *hwmgr;

	int ret, ret1;

	struct pp_instance *pp_handle = (struct pp_instance *)handle;
@@ -241,15 +233,15 @@ static int pp_resume(void *handle) 
	if (ret1 != 0 && ret1 != PP_DPM_DISABLED)

		return ret1;



	smumgr = pp_handle->smu_mgr;

	hwmgr = pp_handle->hwmgr;



	if (smumgr->smumgr_funcs->start_smu == NULL)

	if (hwmgr->smumgr_funcs->start_smu == NULL)

		return -EINVAL;



	ret = smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr);

	ret = hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr);

	if (ret) {

		pr_err("smc start failed\n");

		smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);

		hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);

		return ret;

	}
@@ -1157,13 +1149,9 @@ int amd_powerplay_destroy(void *handle) 
{

	struct pp_instance *instance = (struct pp_instance *)handle;



	if (instance->pm_en) {

	kfree(instance->hwmgr);

	instance->hwmgr = NULL;

	}



	kfree(instance->smu_mgr);

	instance->smu_mgr = NULL;

	kfree(instance);

	instance = NULL;

	return 0;
@@ -1174,7 +1162,7 @@ int amd_powerplay_reset(void *handle) 
	struct pp_instance *instance = (struct pp_instance *)handle;

	int ret;



	if (cgs_is_virtualization_enabled(instance->smu_mgr->device))

	if (cgs_is_virtualization_enabled(instance->hwmgr->device))

		return PP_DPM_DISABLED;



	ret = pp_check(instance);

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+18 −1
Original line number Diff line number Diff line
@@ -37,6 +37,15 @@ 
#include "amd_acpi.h"

#include "pp_psm.h"



extern const struct pp_smumgr_func ci_smu_funcs;

extern const struct pp_smumgr_func cz_smu_funcs;

extern const struct pp_smumgr_func iceland_smu_funcs;

extern const struct pp_smumgr_func tonga_smu_funcs;

extern const struct pp_smumgr_func fiji_smu_funcs;

extern const struct pp_smumgr_func polaris10_smu_funcs;

extern const struct pp_smumgr_func vega10_smu_funcs;

extern const struct pp_smumgr_func rv_smu_funcs;



extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);

static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);

static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
@@ -132,7 +141,6 @@ int hwmgr_early_init(struct pp_instance *handle) 
		return -ENOMEM;



	handle->hwmgr = hwmgr;

	hwmgr->smumgr = handle->smu_mgr;

	hwmgr->device = handle->device;

	hwmgr->chip_family = handle->chip_family;

	hwmgr->chip_id = handle->chip_id;
@@ -144,9 +152,11 @@ int hwmgr_early_init(struct pp_instance *handle) 
	hwmgr_init_default_caps(hwmgr);

	hwmgr_set_user_specify_caps(hwmgr);

	hwmgr->fan_ctrl_is_in_default_mode = true;

	hwmgr->reload_fw = 1;



	switch (hwmgr->chip_family) {

	case AMDGPU_FAMILY_CI:

		hwmgr->smumgr_funcs = &ci_smu_funcs;

		ci_set_asic_special_caps(hwmgr);

		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |

					PP_ENABLE_GFX_CG_THRU_SMU);
@@ -154,21 +164,25 @@ int hwmgr_early_init(struct pp_instance *handle) 
		smu7_init_function_pointers(hwmgr);

		break;

	case AMDGPU_FAMILY_CZ:

		hwmgr->smumgr_funcs = &cz_smu_funcs;

		cz_init_function_pointers(hwmgr);

		break;

	case AMDGPU_FAMILY_VI:

		switch (hwmgr->chip_id) {

		case CHIP_TOPAZ:

			hwmgr->smumgr_funcs = &iceland_smu_funcs;

			topaz_set_asic_special_caps(hwmgr);

			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |

						PP_ENABLE_GFX_CG_THRU_SMU);

			hwmgr->pp_table_version = PP_TABLE_V0;

			break;

		case CHIP_TONGA:

			hwmgr->smumgr_funcs = &tonga_smu_funcs;

			tonga_set_asic_special_caps(hwmgr);

			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;

			break;

		case CHIP_FIJI:

			hwmgr->smumgr_funcs = &fiji_smu_funcs;

			fiji_set_asic_special_caps(hwmgr);

			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |

						PP_ENABLE_GFX_CG_THRU_SMU);
@@ -176,6 +190,7 @@ int hwmgr_early_init(struct pp_instance *handle) 
		case CHIP_POLARIS11:

		case CHIP_POLARIS10:

		case CHIP_POLARIS12:

			hwmgr->smumgr_funcs = &polaris10_smu_funcs;

			polaris_set_asic_special_caps(hwmgr);

			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);

			break;
@@ -187,6 +202,7 @@ int hwmgr_early_init(struct pp_instance *handle) 
	case AMDGPU_FAMILY_AI:

		switch (hwmgr->chip_id) {

		case CHIP_VEGA10:

			hwmgr->smumgr_funcs = &vega10_smu_funcs;

			vega10_hwmgr_init(hwmgr);

			break;

		default:
@@ -196,6 +212,7 @@ int hwmgr_early_init(struct pp_instance *handle) 
	case AMDGPU_FAMILY_RV:

		switch (hwmgr->chip_id) {

		case CHIP_RAVEN:

			hwmgr->smumgr_funcs = &rv_smu_funcs;

			rv_init_function_pointers(hwmgr);

			break;

		default:

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+2 −2
Original line number Diff line number Diff line
@@ -1382,7 +1382,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 
	data->force_pcie_gen = PP_PCIEGenInvalid;

	data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;



	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) {

	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {

		uint8_t tmp1, tmp2;

		uint16_t tmp3 = 0;

		atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
@@ -4623,7 +4623,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, 


static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)

{

	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);

	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);



	if (smu_data == NULL)

		return -EINVAL;

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c

+1 −1
Original line number Diff line number Diff line
@@ -763,7 +763,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) 
			} else if (hwmgr->chip_id == CHIP_POLARIS11) {

				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);

				PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);

				if (hwmgr->smumgr->is_kicker)

				if (hwmgr->is_kicker)

					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);

				else

					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+40 −0
Original line number Diff line number Diff line
@@ -235,6 +235,39 @@ struct phm_vce_clock_voltage_dependency_table { 
	struct phm_vce_clock_voltage_dependency_record entries[1];

};



struct pp_smumgr_func {

	int (*smu_init)(struct pp_hwmgr  *hwmgr);

	int (*smu_fini)(struct pp_hwmgr  *hwmgr);

	int (*start_smu)(struct pp_hwmgr  *hwmgr);

	int (*check_fw_load_finish)(struct pp_hwmgr  *hwmgr,

				    uint32_t firmware);

	int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);

	int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,

					    uint32_t firmware);

	int (*get_argument)(struct pp_hwmgr  *hwmgr);

	int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);

	int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,

					  uint16_t msg, uint32_t parameter);

	int (*download_pptable_settings)(struct pp_hwmgr  *hwmgr,

					 void **table);

	int (*upload_pptable_settings)(struct pp_hwmgr  *hwmgr);

	int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);

	int (*process_firmware_header)(struct pp_hwmgr *hwmgr);

	int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);

	int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);

	int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);

	int (*init_smc_table)(struct pp_hwmgr *hwmgr);

	int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);

	int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);

	int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);

	uint32_t (*get_offsetof)(uint32_t type, uint32_t member);

	uint32_t (*get_mac_definition)(uint32_t value);

	bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);

	int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,

			struct amd_pp_profile *request);

	bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);

};



struct pp_hwmgr_func {

	int (*backend_init)(struct pp_hwmgr *hw_mgr);

	int (*backend_fini)(struct pp_hwmgr *hw_mgr);
@@ -706,10 +739,17 @@ struct pp_hwmgr { 
	void *pptable;

	struct phm_platform_descriptor platform_descriptor;

	void *backend;



	void *smu_backend;

	const struct pp_smumgr_func *smumgr_funcs;

	bool is_kicker;

	bool reload_fw;



	enum PP_DAL_POWERLEVEL dal_power_level;

	struct phm_dynamic_state_info dyn_state;

	const struct pp_hwmgr_func *hwmgr_func;

	const struct pp_table_func *pptable_func;



	struct pp_power_state    *ps;

	enum pp_power_source  power_source;

	uint32_t num_ps;

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