Commit b37665e0 authored by Andy Fleming's avatar Andy Fleming Committed by Paul Mackerras
Browse files

[PATCH] ppc32: 85xx PHY Platform Update 



This patch updates the 85xx platform code to support the new PHY Layer.

Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
Signed-off-by: default avatarKumar Gala <Kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent dd03d25f

arch/ppc/platforms/85xx/mpc8540_ads.c

+18 −12
Original line number Diff line number Diff line
@@ -52,6 +52,10 @@ 


#include <syslib/ppc85xx_setup.h>



static const char *GFAR_PHY_0 = "phy0:0";

static const char *GFAR_PHY_1 = "phy0:1";

static const char *GFAR_PHY_3 = "phy0:3";



/* ************************************************************************

 *

 * Setup the architecture
@@ -63,6 +67,7 @@ mpc8540ads_setup_arch(void) 
	bd_t *binfo = (bd_t *) __res;

	unsigned int freq;

	struct gianfar_platform_data *pdata;

	struct gianfar_mdio_data *mdata;



	/* get the core frequency */

	freq = binfo->bi_intfreq;
@@ -89,34 +94,35 @@ mpc8540ads_setup_arch(void) 
	invalidate_tlbcam_entry(num_tlbcam_entries - 1);

#endif



	/* setup the board related info for the MDIO bus */

	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);



	mdata->irq[0] = MPC85xx_IRQ_EXT5;

	mdata->irq[1] = MPC85xx_IRQ_EXT5;

	mdata->irq[2] = -1;

	mdata->irq[3] = MPC85xx_IRQ_EXT5;

	mdata->irq[31] = -1;

	mdata->paddr += binfo->bi_immr_base;



	/* setup the board related information for the enet controllers */

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 0;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_0;

		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 1;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_1;

		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);

	if (pdata) {

		pdata->board_flags = 0;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 3;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_3;

		memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);

	}

arch/ppc/platforms/85xx/mpc8560_ads.c

+17 −8
Original line number Diff line number Diff line
@@ -56,6 +56,10 @@ 
#include <syslib/ppc85xx_setup.h>





static const char *GFAR_PHY_0 = "phy0:0";

static const char *GFAR_PHY_1 = "phy0:1";

static const char *GFAR_PHY_3 = "phy0:3";



/* ************************************************************************

 *

 * Setup the architecture
@@ -68,6 +72,7 @@ mpc8560ads_setup_arch(void) 
	bd_t *binfo = (bd_t *) __res;

	unsigned int freq;

	struct gianfar_platform_data *pdata;

	struct gianfar_mdio_data *mdata;



	cpm2_reset();
@@ -86,24 +91,28 @@ mpc8560ads_setup_arch(void) 
	mpc85xx_setup_hose();

#endif



	/* setup the board related info for the MDIO bus */

	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);



	mdata->irq[0] = MPC85xx_IRQ_EXT5;

	mdata->irq[1] = MPC85xx_IRQ_EXT5;

	mdata->irq[2] = -1;

	mdata->irq[3] = MPC85xx_IRQ_EXT5;

	mdata->irq[31] = -1;

	mdata->paddr += binfo->bi_immr_base;



	/* setup the board related information for the enet controllers */

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 0;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_0;

		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 1;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_1;

		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);

	}

arch/ppc/platforms/85xx/mpc85xx_cds_common.c

+18 −16
Original line number Diff line number Diff line
@@ -391,6 +391,9 @@ mpc85xx_cds_pcibios_fixup(void) 


TODC_ALLOC();



static const char *GFAR_PHY_0 = "phy0:0";

static const char *GFAR_PHY_1 = "phy0:1";



/* ************************************************************************

 *

 * Setup the architecture
@@ -402,6 +405,7 @@ mpc85xx_cds_setup_arch(void) 
	bd_t *binfo = (bd_t *) __res;

	unsigned int freq;

	struct gianfar_platform_data *pdata;

	struct gianfar_mdio_data *mdata;



	/* get the core frequency */

	freq = binfo->bi_intfreq;
@@ -445,44 +449,42 @@ mpc85xx_cds_setup_arch(void) 
	invalidate_tlbcam_entry(num_tlbcam_entries - 1);

#endif



	/* setup the board related info for the MDIO bus */

	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);



	mdata->irq[0] = MPC85xx_IRQ_EXT5;

	mdata->irq[1] = MPC85xx_IRQ_EXT5;

	mdata->irq[2] = -1;

	mdata->irq[3] = -1;

	mdata->irq[31] = -1;

	mdata->paddr += binfo->bi_immr_base;



	/* setup the board related information for the enet controllers */

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 0;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_0;

		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 1;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_1;

		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 0;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_0;

		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 1;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_1;

		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);

	}

arch/ppc/platforms/85xx/sbc8560.c

+14 −8
Original line number Diff line number Diff line
@@ -91,6 +91,9 @@ sbc8560_early_serial_map(void) 
}

#endif



static const char *GFAR_PHY_25 = "phy0:25";

static const char *GFAR_PHY_26 = "phy0:26";



/* ************************************************************************

 *

 * Setup the architecture
@@ -102,6 +105,7 @@ sbc8560_setup_arch(void) 
	bd_t *binfo = (bd_t *) __res;

	unsigned int freq;

	struct gianfar_platform_data *pdata;

	struct gianfar_mdio_data *mdata;



	/* get the core frequency */

	freq = binfo->bi_intfreq;
@@ -126,24 +130,26 @@ sbc8560_setup_arch(void) 
	invalidate_tlbcam_entry(num_tlbcam_entries - 1);

#endif



	/* setup the board related info for the MDIO bus */

	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);



	mdata->irq[25] = MPC85xx_IRQ_EXT6;

	mdata->irq[26] = MPC85xx_IRQ_EXT7;

	mdata->irq[31] = -1;

	mdata->paddr += binfo->bi_immr_base;



	/* setup the board related information for the enet controllers */

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT6;

		pdata->phyid = 25;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_25;

		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);

	if (pdata) {

		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;

		pdata->interruptPHY = MPC85xx_IRQ_EXT7;

		pdata->phyid = 26;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_26;

		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);

	}

arch/ppc/platforms/85xx/stx_gp3.c

+14 −7
Original line number Diff line number Diff line
@@ -91,6 +91,9 @@ static u8 gp3_openpic_initsenses[] __initdata = { 
	0x0,				/* External 11: */

};



static const char *GFAR_PHY_2 = "phy0:2";

static const char *GFAR_PHY_4 = "phy0:4";



/*

 * Setup the architecture

 */
@@ -100,6 +103,7 @@ gp3_setup_arch(void) 
	bd_t *binfo = (bd_t *) __res;

	unsigned int freq;

	struct gianfar_platform_data *pdata;

	struct gianfar_mdio_data *mdata;



	cpm2_reset();
@@ -118,23 +122,26 @@ gp3_setup_arch(void) 
	mpc85xx_setup_hose();

#endif



	/* setup the board related info for the MDIO bus */

	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);



	mdata->irq[2] = MPC85xx_IRQ_EXT5;

	mdata->irq[4] = MPC85xx_IRQ_EXT5;

	mdata->irq[31] = -1;

	mdata->paddr += binfo->bi_immr_base;



	/* setup the board related information for the enet controllers */

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);

	if (pdata) {

	/*	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 2;

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_2;

		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);

	}



	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);

	if (pdata) {

	/*	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */

		pdata->interruptPHY = MPC85xx_IRQ_EXT5;

		pdata->phyid = 4;

		/* fixup phy address */

		pdata->phy_reg_addr += binfo->bi_immr_base;

		pdata->bus_id = GFAR_PHY_4;

		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);

	}

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