Commit b3727c24 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-fixes-for-linus' of... 

Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86: Print the hypervisor returned tsc_khz during boot
  x86: Correct segment permission flags in 64-bit linker script
  x86: cpuinit-annotate SMP boot trampolines properly
  x86: Increase timeout for EHCI debug port reset completion in early printk
  x86: Fix uaccess_32.h typo
  x86: Trivial whitespace cleanups
  x86, apic: Fix missed handling of discrete apics
  x86/i386: Remove duplicated #include
  x86, mtrr: Convert loop to a while based construct, avoid naked semicolon
  Revert 'x86: Fix system crash when loading with "reservetop" parameter'
  x86, mce: Fix compile warning in case of CONFIG_SMP=n
  x86, apic: Use logical flat on intel with <= 8 logical cpus
  x86: SGI UV: Map MMIO-High memory range
  x86: SGI UV: Add volatile semantics to macros that access chipset registers
  x86: SGI UV: Fix IPI macros
  x86: apic: Convert BUG() to BUG_ON()
  x86: Remove final bits of CONFIG_X86_OLD_MCE
parents 58e75a09 6399c087

arch/x86/include/asm/apic.h

+13 −0
Original line number Diff line number Diff line
@@ -65,6 +65,19 @@ static inline void default_inquire_remote_apic(int apicid) 
		__inquire_remote_apic(apicid);

}



/*

 * With 82489DX we can't rely on apic feature bit

 * retrieved via cpuid but still have to deal with

 * such an apic chip so we assume that SMP configuration

 * is found from MP table (64bit case uses ACPI mostly

 * which set smp presence flag as well so we are safe

 * to use this helper too).

 */

static inline bool apic_from_smp_config(void)

{

	return smp_found_config && !disable_apic;

}



/*

 * Basic functions accessing APICs.

 */

arch/x86/include/asm/string_32.h

+0 −1
Original line number Diff line number Diff line
@@ -65,7 +65,6 @@ static __always_inline void *__constant_memcpy(void *to, const void *from, 
	case 4:

		*(int *)to = *(int *)from;

		return to;



	case 3:

		*(short *)to = *(short *)from;

		*((char *)to + 2) = *((char *)from + 2);

arch/x86/include/asm/uaccess_32.h

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ unsigned long __must_check __copy_from_user_ll_nocache_nozero 
 * Copy data from kernel space to user space.  Caller must check

 * the specified block with access_ok() before calling this function.

 * The caller should also make sure he pins the user space address

 * so that the we don't result in page fault and sleep.

 * so that we don't result in page fault and sleep.

 *

 * Here we special-case 1, 2 and 4-byte copy_*_user invocations.  On a fault

 * we return the initial request size (1, 2 or 4), as copy_*_user should do.

arch/x86/include/asm/uv/uv_hub.h

+10 −9
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/numa.h>

#include <linux/percpu.h>

#include <linux/timer.h>

#include <linux/io.h>

#include <asm/types.h>

#include <asm/percpu.h>

#include <asm/uv/uv_mmrs.h>
@@ -258,13 +259,13 @@ static inline unsigned long *uv_global_mmr32_address(int pnode, 
static inline void uv_write_global_mmr32(int pnode, unsigned long offset,

				 unsigned long val)

{

	*uv_global_mmr32_address(pnode, offset) = val;

	writeq(val, uv_global_mmr32_address(pnode, offset));

}



static inline unsigned long uv_read_global_mmr32(int pnode,

						 unsigned long offset)

{

	return *uv_global_mmr32_address(pnode, offset);

	return readq(uv_global_mmr32_address(pnode, offset));

}



/*
@@ -281,13 +282,13 @@ static inline unsigned long *uv_global_mmr64_address(int pnode, 
static inline void uv_write_global_mmr64(int pnode, unsigned long offset,

				unsigned long val)

{

	*uv_global_mmr64_address(pnode, offset) = val;

	writeq(val, uv_global_mmr64_address(pnode, offset));

}



static inline unsigned long uv_read_global_mmr64(int pnode,

						 unsigned long offset)

{

	return *uv_global_mmr64_address(pnode, offset);

	return readq(uv_global_mmr64_address(pnode, offset));

}



/*
@@ -301,22 +302,22 @@ static inline unsigned long *uv_local_mmr_address(unsigned long offset) 


static inline unsigned long uv_read_local_mmr(unsigned long offset)

{

	return *uv_local_mmr_address(offset);

	return readq(uv_local_mmr_address(offset));

}



static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)

{

	*uv_local_mmr_address(offset) = val;

	writeq(val, uv_local_mmr_address(offset));

}



static inline unsigned char uv_read_local_mmr8(unsigned long offset)

{

	return *((unsigned char *)uv_local_mmr_address(offset));

	return readb(uv_local_mmr_address(offset));

}



static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)

{

	*((unsigned char *)uv_local_mmr_address(offset)) = val;

	writeb(val, uv_local_mmr_address(offset));

}



/*
@@ -422,7 +423,7 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 
	unsigned long val;



	val = (1UL << UVH_IPI_INT_SEND_SHFT) |

			((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) |

			((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |

			(vector << UVH_IPI_INT_VECTOR_SHFT);

	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);

}

arch/x86/kernel/apic/apic.c

+10 −21
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ unsigned int boot_cpu_physical_apicid = -1U; 
/*

 * The highest APIC ID seen during enumeration.

 *

 * This determines the messaging protocol we can use: if all APIC IDs

 * On AMD, this determines the messaging protocol we can use: if all APIC IDs

 * are in the 0 ... 7 range, then we can use logical addressing which

 * has some performance advantages (better broadcasting).

 *
@@ -979,7 +979,7 @@ void lapic_shutdown(void) 
{

	unsigned long flags;



	if (!cpu_has_apic)

	if (!cpu_has_apic && !apic_from_smp_config())

		return;



	local_irq_save(flags);
@@ -1197,8 +1197,7 @@ void __cpuinit setup_local_APIC(void) 
	 * Double-check whether this APIC is really registered.

	 * This is meaningless in clustered apic mode, so we skip it.

	 */

	if (!apic->apic_id_registered())

		BUG();

	BUG_ON(!apic->apic_id_registered());



	/*

	 * Intel recommends to set DFR, LDR and TPR before enabling
@@ -1917,25 +1916,15 @@ void __cpuinit generic_processor_info(int apicid, int version) 
		max_physical_apicid = apicid;



#ifdef CONFIG_X86_32

	/*

	 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y

	 * but we need to work other dependencies like SMP_SUSPEND etc

	 * before this can be done without some confusion.

	 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)

	 *       - Ashok Raj <ashok.raj@intel.com>

	 */

	if (max_physical_apicid >= 8) {

	switch (boot_cpu_data.x86_vendor) {

	case X86_VENDOR_INTEL:

			if (!APIC_XAPIC(version)) {

				def_to_bigsmp = 0;

		if (num_processors > 8)

			def_to_bigsmp = 1;

		break;

			}

			/* If P4 and above fall through */

	case X86_VENDOR_AMD:

		if (max_physical_apicid >= 8)

			def_to_bigsmp = 1;

	}

	}

#endif



#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)

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