Commit b36d3c0f authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
Browse files

can: flexcan: rename macro FLEXCAN_IFLAG_MB() -> FLEXCAN_IFLAG2_MB()



The macro FLEXCAN_IFLAG_MB() is always used for the iflag2 register, so
rename it to FLEXCAN_IFLAG2_MB()

Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 58ed8e77
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+5 −5
Original line number Original line Diff line number Diff line
@@ -142,7 +142,7 @@
#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO		8
#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO		8
#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP	0
#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP	0
#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST	(FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST	(FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
#define FLEXCAN_IFLAG_MB(x)		BIT((x) & 0x1f)
#define FLEXCAN_IFLAG2_MB(x)		BIT((x) & 0x1f)
#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
#define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
#define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)
#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)
@@ -879,7 +879,7 @@ static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
	u32 iflag1, iflag2;
	u32 iflag1, iflag2;


	iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
	iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
		~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
		~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
	iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
	iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;


	return (u64)iflag2 << 32 | iflag1;
	return (u64)iflag2 << 32 | iflag1;
@@ -929,7 +929,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
	reg_iflag2 = priv->read(&regs->iflag2);
	reg_iflag2 = priv->read(&regs->iflag2);


	/* transmission complete interrupt */
	/* transmission complete interrupt */
	if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
	if (reg_iflag2 & FLEXCAN_IFLAG2_MB(priv->tx_mb_idx)) {
		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);


		handled = IRQ_HANDLED;
		handled = IRQ_HANDLED;
@@ -941,7 +941,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
		/* after sending a RTR frame MB is in RX mode */
		/* after sending a RTR frame MB is in RX mode */
		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
			    &priv->tx_mb->can_ctrl);
			    &priv->tx_mb->can_ctrl);
		priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
		priv->write(FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), &regs->iflag2);
		netif_wake_queue(dev);
		netif_wake_queue(dev);
	}
	}


@@ -1298,7 +1298,7 @@ static int flexcan_open(struct net_device *dev)
	priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
	priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);


	priv->reg_imask1_default = 0;
	priv->reg_imask1_default = 0;
	priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
	priv->reg_imask2_default = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);


	priv->offload.mailbox_read = flexcan_mailbox_read;
	priv->offload.mailbox_read = flexcan_mailbox_read;