dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier PCIe PHY

description: |

  This describes the devicetree bindings for PHY interface built into

  PCIe controller implemented on Socionext UniPhier SoCs.

maintainers:

  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

properties:

  compatible:

    enum:

      - socionext,uniphier-pro5-pcie-phy

      - socionext,uniphier-ld20-pcie-phy

      - socionext,uniphier-pxs3-pcie-phy

  reg:

    description: PHY register region (offset and length)

  "#phy-cells":

    const: 0

  clocks:

    minItems: 1

    maxItems: 2

  clock-names:

    oneOf:

      - items:            # for Pro5

        - const: gio

        - const: link

      - const: link       # for others

  resets:

    minItems: 1

    maxItems: 2

  reset-names:

    oneOf:

      - items:            # for Pro5

        - const: gio

        - const: link

      - const: link       # for others

  socionext,syscon:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: A phandle to system control to set configurations for phy

required:

  - compatible

  - reg

  - "#phy-cells"

  - clocks

  - clock-names

  - resets

  - reset-names

additionalProperties: false

examples:

  - |

    pcie_phy: phy@66038000 {

        compatible = "socionext,uniphier-ld20-pcie-phy";

        reg = <0x66038000 0x4000>;

        #phy-cells = <0>;

        clock-names = "link";

        clocks = <&sys_clk 24>;

        reset-names = "link";

        resets = <&sys_rst 24>;

        socionext,syscon = <&soc_glue>;

    };

Socionext UniPhier PCIe PHY bindings

This describes the devicetree bindings for PHY interface built into

PCIe controller implemented on Socionext UniPhier SoCs.

Required properties:

- compatible: Should contain one of the following:

    "socionext,uniphier-pro5-pcie-phy" - for Pro5 PHY

    "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY

    "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY

- reg: Specifies offset and length of the register set for the device.

- #phy-cells: Must be zero.

- clocks: A list of phandles to the clock gate for PCIe glue layer

	including this phy.

- clock-names: For Pro5 only, should contain the following:

    "gio", "link" - for Pro5 SoC

- resets: A list of phandles to the reset line for PCIe glue layer

	including this phy.

- reset-names: For Pro5 only, should contain the following:

    "gio", "link" - for Pro5 SoC

Optional properties:

- socionext,syscon: A phandle to system control to set configurations

	for phy.

Refer to phy/phy-bindings.txt for the generic PHY binding properties.

Example:

	pcie_phy: phy@66038000 {

		compatible = "socionext,uniphier-ld20-pcie-phy";

		reg = <0x66038000 0x4000>;

		#phy-cells = <0>;

		clocks = <&sys_clk 24>;

		resets = <&sys_rst 24>;

		socionext,syscon = <&soc_glue>;

	};