Commit b334ec66 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'Fix-broken-tc-flower-rules-for-mscc_ocelot-switches'



Vladimir Oltean says:

====================
Fix broken tc-flower rules for mscc_ocelot switches

All 3 switch drivers from the Ocelot family have the same bug in the
VCAP IS2 key offsets, which is that some keys are in the incorrect
order.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d5e4d0a5 8194d8fa
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+8 −8
Original line number Diff line number Diff line
@@ -645,17 +645,17 @@ static struct vcap_field vsc9959_vcap_is2_keys[] = {
	[VCAP_IS2_HK_DIP_EQ_SIP]		= {118,   1},
	/* IP4_TCP_UDP (TYPE=100) */
	[VCAP_IS2_HK_TCP]			= {119,   1},
	[VCAP_IS2_HK_L4_SPORT]			= {120,  16},
	[VCAP_IS2_HK_L4_DPORT]			= {136,  16},
	[VCAP_IS2_HK_L4_DPORT]			= {120,  16},
	[VCAP_IS2_HK_L4_SPORT]			= {136,  16},
	[VCAP_IS2_HK_L4_RNG]			= {152,   8},
	[VCAP_IS2_HK_L4_SPORT_EQ_DPORT]		= {160,   1},
	[VCAP_IS2_HK_L4_SEQUENCE_EQ0]		= {161,   1},
	[VCAP_IS2_HK_L4_URG]			= {162,   1},
	[VCAP_IS2_HK_L4_ACK]			= {163,   1},
	[VCAP_IS2_HK_L4_PSH]			= {164,   1},
	[VCAP_IS2_HK_L4_RST]			= {165,   1},
	[VCAP_IS2_HK_L4_SYN]			= {166,   1},
	[VCAP_IS2_HK_L4_FIN]			= {167,   1},
	[VCAP_IS2_HK_L4_FIN]			= {162,   1},
	[VCAP_IS2_HK_L4_SYN]			= {163,   1},
	[VCAP_IS2_HK_L4_RST]			= {164,   1},
	[VCAP_IS2_HK_L4_PSH]			= {165,   1},
	[VCAP_IS2_HK_L4_ACK]			= {166,   1},
	[VCAP_IS2_HK_L4_URG]			= {167,   1},
	[VCAP_IS2_HK_L4_1588_DOM]		= {168,   8},
	[VCAP_IS2_HK_L4_1588_VER]		= {176,   4},
	/* IP4_OTHER (TYPE=101) */
+8 −8
Original line number Diff line number Diff line
@@ -659,17 +659,17 @@ static struct vcap_field vsc9953_vcap_is2_keys[] = {
	[VCAP_IS2_HK_DIP_EQ_SIP]		= {122,   1},
	/* IP4_TCP_UDP (TYPE=100) */
	[VCAP_IS2_HK_TCP]			= {123,   1},
	[VCAP_IS2_HK_L4_SPORT]			= {124,  16},
	[VCAP_IS2_HK_L4_DPORT]			= {140,  16},
	[VCAP_IS2_HK_L4_DPORT]			= {124,  16},
	[VCAP_IS2_HK_L4_SPORT]			= {140,  16},
	[VCAP_IS2_HK_L4_RNG]			= {156,   8},
	[VCAP_IS2_HK_L4_SPORT_EQ_DPORT]		= {164,   1},
	[VCAP_IS2_HK_L4_SEQUENCE_EQ0]		= {165,   1},
	[VCAP_IS2_HK_L4_URG]			= {166,   1},
	[VCAP_IS2_HK_L4_ACK]			= {167,   1},
	[VCAP_IS2_HK_L4_PSH]			= {168,   1},
	[VCAP_IS2_HK_L4_RST]			= {169,   1},
	[VCAP_IS2_HK_L4_SYN]			= {170,   1},
	[VCAP_IS2_HK_L4_FIN]			= {171,   1},
	[VCAP_IS2_HK_L4_FIN]			= {166,   1},
	[VCAP_IS2_HK_L4_SYN]			= {167,   1},
	[VCAP_IS2_HK_L4_RST]			= {168,   1},
	[VCAP_IS2_HK_L4_PSH]			= {169,   1},
	[VCAP_IS2_HK_L4_ACK]			= {170,   1},
	[VCAP_IS2_HK_L4_URG]			= {171,   1},
	/* IP4_OTHER (TYPE=101) */
	[VCAP_IS2_HK_IP4_L3_PROTO]		= {123,   8},
	[VCAP_IS2_HK_L3_PAYLOAD]		= {131,  56},
+8 −8
Original line number Diff line number Diff line
@@ -806,17 +806,17 @@ static const struct vcap_field vsc7514_vcap_is2_keys[] = {
	[VCAP_IS2_HK_DIP_EQ_SIP]		= {123,   1},
	/* IP4_TCP_UDP (TYPE=100) */
	[VCAP_IS2_HK_TCP]			= {124,   1},
	[VCAP_IS2_HK_L4_SPORT]			= {125,  16},
	[VCAP_IS2_HK_L4_DPORT]			= {141,  16},
	[VCAP_IS2_HK_L4_DPORT]			= {125,  16},
	[VCAP_IS2_HK_L4_SPORT]			= {141,  16},
	[VCAP_IS2_HK_L4_RNG]			= {157,   8},
	[VCAP_IS2_HK_L4_SPORT_EQ_DPORT]		= {165,   1},
	[VCAP_IS2_HK_L4_SEQUENCE_EQ0]		= {166,   1},
	[VCAP_IS2_HK_L4_URG]			= {167,   1},
	[VCAP_IS2_HK_L4_ACK]			= {168,   1},
	[VCAP_IS2_HK_L4_PSH]			= {169,   1},
	[VCAP_IS2_HK_L4_RST]			= {170,   1},
	[VCAP_IS2_HK_L4_SYN]			= {171,   1},
	[VCAP_IS2_HK_L4_FIN]			= {172,   1},
	[VCAP_IS2_HK_L4_FIN]			= {167,   1},
	[VCAP_IS2_HK_L4_SYN]			= {168,   1},
	[VCAP_IS2_HK_L4_RST]			= {169,   1},
	[VCAP_IS2_HK_L4_PSH]			= {170,   1},
	[VCAP_IS2_HK_L4_ACK]			= {171,   1},
	[VCAP_IS2_HK_L4_URG]			= {172,   1},
	[VCAP_IS2_HK_L4_1588_DOM]		= {173,   8},
	[VCAP_IS2_HK_L4_1588_VER]		= {181,   4},
	/* IP4_OTHER (TYPE=101) */