Commit b3282738 authored by George Shen's avatar George Shen Committed by Alex Deucher
Browse files

drm/amd/display: Move USB-C workaround to after parameter variables are set 



[Why]
The call to dp_enable_link_phy are using default/invalid values for clock id
and link settings.

[How]
Move workaround code to after its parameter variables are determined.

Signed-off-by: default avatarGeorge Shen <george.shen@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d4b8573e

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+10 −9
Original line number Diff line number Diff line
@@ -1892,6 +1892,16 @@ bool dp_verify_link_cap( 
	/* disable PHY done possible by BIOS, will be done by driver itself */

	dp_disable_link_phy(link, link->connector_signal);



	dp_cs_id = get_clock_source_id(link);



	/* link training starts with the maximum common settings

	 * supported by both sink and ASIC.

	 */

	initial_link_settings = get_common_supported_link_settings(

			*known_limit_link_setting,

			max_link_cap);

	cur_link_setting = initial_link_settings;



	/* Temporary Renoir-specific workaround for SWDEV-215184;

	 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,

	 * so add extra cycle of enabling and disabling the PHY before first link training.
@@ -1902,15 +1912,6 @@ bool dp_verify_link_cap( 
		dp_disable_link_phy(link, link->connector_signal);

	}



	dp_cs_id = get_clock_source_id(link);



	/* link training starts with the maximum common settings

	 * supported by both sink and ASIC.

	 */

	initial_link_settings = get_common_supported_link_settings(

			*known_limit_link_setting,

			max_link_cap);

	cur_link_setting = initial_link_settings;

	do {

		skip_video_pattern = true;

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