Commit b325e04e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpufeature updates from Thomas Gleixner:

 - a workaround for the MONITOR instruction erratum of Goldmont CPUs

 - small fixes and cleanups here and there

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Add workaround for MONITOR instruction erratum on Goldmont based CPUs
  x86/cpu: Rename "WESTMERE2" family to "NEHALEM_G"
  x86/amd_nb: Clean up init path
  x86/cpufeature: Add helper macro for mask check macros
  x86/cpufeature: Make sure DISABLED/REQUIRED macros are updated
  x86/cpufeature: Update cpufeaure macros
parents 7f7d5564 08e237fa

arch/x86/events/msr.c

+1 −1
Original line number Diff line number Diff line
@@ -36,11 +36,11 @@ static bool test_intel(int idx) 


	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_NEHALEM:

	case INTEL_FAM6_NEHALEM_G:

	case INTEL_FAM6_NEHALEM_EP:

	case INTEL_FAM6_NEHALEM_EX:



	case INTEL_FAM6_WESTMERE:

	case INTEL_FAM6_WESTMERE2:

	case INTEL_FAM6_WESTMERE_EP:

	case INTEL_FAM6_WESTMERE_EX:

arch/x86/include/asm/cpufeature.h

+53 −37
Original line number Diff line number Diff line
@@ -49,43 +49,59 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
#define test_cpu_cap(c, bit)						\

	 test_bit(bit, (unsigned long *)((c)->x86_capability))



#define REQUIRED_MASK_BIT_SET(bit)					\

	 ( (((bit)>>5)==0  && (1UL<<((bit)&31) & REQUIRED_MASK0 )) ||	\

	   (((bit)>>5)==1  && (1UL<<((bit)&31) & REQUIRED_MASK1 )) ||	\

	   (((bit)>>5)==2  && (1UL<<((bit)&31) & REQUIRED_MASK2 )) ||	\

	   (((bit)>>5)==3  && (1UL<<((bit)&31) & REQUIRED_MASK3 )) ||	\

	   (((bit)>>5)==4  && (1UL<<((bit)&31) & REQUIRED_MASK4 )) ||	\

	   (((bit)>>5)==5  && (1UL<<((bit)&31) & REQUIRED_MASK5 )) ||	\

	   (((bit)>>5)==6  && (1UL<<((bit)&31) & REQUIRED_MASK6 )) ||	\

	   (((bit)>>5)==7  && (1UL<<((bit)&31) & REQUIRED_MASK7 )) ||	\

	   (((bit)>>5)==8  && (1UL<<((bit)&31) & REQUIRED_MASK8 )) ||	\

	   (((bit)>>5)==9  && (1UL<<((bit)&31) & REQUIRED_MASK9 )) ||	\

	   (((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) ||	\

	   (((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) ||	\

	   (((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) ||	\

	   (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) ||	\

	   (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK14)) ||	\

	   (((bit)>>5)==15 && (1UL<<((bit)&31) & REQUIRED_MASK15)) ||	\

	   (((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) )



#define DISABLED_MASK_BIT_SET(bit)					\

	 ( (((bit)>>5)==0  && (1UL<<((bit)&31) & DISABLED_MASK0 )) ||	\

	   (((bit)>>5)==1  && (1UL<<((bit)&31) & DISABLED_MASK1 )) ||	\

	   (((bit)>>5)==2  && (1UL<<((bit)&31) & DISABLED_MASK2 )) ||	\

	   (((bit)>>5)==3  && (1UL<<((bit)&31) & DISABLED_MASK3 )) ||	\

	   (((bit)>>5)==4  && (1UL<<((bit)&31) & DISABLED_MASK4 )) ||	\

	   (((bit)>>5)==5  && (1UL<<((bit)&31) & DISABLED_MASK5 )) ||	\

	   (((bit)>>5)==6  && (1UL<<((bit)&31) & DISABLED_MASK6 )) ||	\

	   (((bit)>>5)==7  && (1UL<<((bit)&31) & DISABLED_MASK7 )) ||	\

	   (((bit)>>5)==8  && (1UL<<((bit)&31) & DISABLED_MASK8 )) ||	\

	   (((bit)>>5)==9  && (1UL<<((bit)&31) & DISABLED_MASK9 )) ||	\

	   (((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) ||	\

	   (((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) ||	\

	   (((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) ||	\

	   (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) ||	\

	   (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK14)) ||	\

	   (((bit)>>5)==15 && (1UL<<((bit)&31) & DISABLED_MASK15)) ||	\

	   (((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) )

/*

 * There are 32 bits/features in each mask word.  The high bits

 * (selected with (bit>>5) give us the word number and the low 5

 * bits give us the bit/feature number inside the word.

 * (1UL<<((bit)&31) gives us a mask for the feature_bit so we can

 * see if it is set in the mask word.

 */

#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit)	\

	(((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word ))



#define REQUIRED_MASK_BIT_SET(feature_bit)		\

	 ( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  0, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  1, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  2, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  3, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  4, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  5, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  6, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  7, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  8, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK,  9, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 10, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 11, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 12, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 13, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 14, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||	\

	   REQUIRED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 18))



#define DISABLED_MASK_BIT_SET(feature_bit)				\

	 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  1, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  2, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  3, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  4, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  5, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  6, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  7, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  8, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  9, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 10, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 11, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 12, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 13, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 14, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||	\

	   DISABLED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 18))



#define cpu_has(c, bit)							\

	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -309,5 +309,5 @@ 
#endif

#define X86_BUG_NULL_SEG	X86_BUG(10) /* Nulling a selector preserves the base */

#define X86_BUG_SWAPGS_FENCE	X86_BUG(11) /* SWAPGS without input dep on GS */



#define X86_BUG_MONITOR		X86_BUG(12) /* IPI required to wake up remote CPU */

#endif /* _ASM_X86_CPUFEATURES_H */

arch/x86/include/asm/disabled-features.h

+2 −0
Original line number Diff line number Diff line
@@ -56,5 +56,7 @@ 
#define DISABLED_MASK14	0

#define DISABLED_MASK15	0

#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE)

#define DISABLED_MASK17	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)



#endif /* _ASM_X86_DISABLED_FEATURES_H */

arch/x86/include/asm/intel-family.h

+2 −2
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 
 * "Extreme" ones, like Broadwell-E.

 *

 * Things ending in "2" are usually because we have no better

 * name for them.  There's no processor called "WESTMERE2".

 * name for them.  There's no processor called "SILVERMONT2".

 */



#define INTEL_FAM6_CORE_YONAH		0x0E
@@ -18,10 +18,10 @@ 
#define INTEL_FAM6_CORE2_DUNNINGTON	0x1D



#define INTEL_FAM6_NEHALEM		0x1E

#define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */

#define INTEL_FAM6_NEHALEM_EP		0x1A

#define INTEL_FAM6_NEHALEM_EX		0x2E

#define INTEL_FAM6_WESTMERE		0x25

#define INTEL_FAM6_WESTMERE2		0x1F

#define INTEL_FAM6_WESTMERE_EP		0x2C

#define INTEL_FAM6_WESTMERE_EX		0x2F

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