Commit b324c67d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull device tree conversions for arm-soc, part 1, from Olof Johansson:
 "The spear3xx, lpc32xx, shmobile and mmp platforms are joining the game
  of booting using device trees, which is a great step forward for them.
  at91 and spear have pretty much completed this process with a huge
  amount of work being put into at91.  The other platforms are
  continuing the process.

  We finally start to see the payback on this investment, as new
  machines are getting supported purely by adding a .dts source file
  that can be completely independent of the kernel source."

Fix up trivial conflict in arch/arm/Kconfig

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
  ARM: at91: Add ADC driver to at91sam9260/at91sam9g20 dtsi files
  arm/dts: omap4-panda: Add LEDs support
  arm/dts: omap4-sdp: Add LEDs support
  arm/dts: twl4030: Add twl4030-gpio node
  OMAP4: devices: Do not create mcpdm device if the dtb has been provided
  OMAP4: devices: Do not create dmic device if the dtb has been provided
  Documentation: update docs for mmp dt
  ARM: dts: refresh dts file for arch mmp
  ARM: mmp: support pxa910 with device tree
  ARM: mmp: support mmp2 with device tree
  gpio: pxa: parse gpio from DTS file
  ARM: mmp: support DT in timer
  ARM: mmp: support DT in irq
  ARM: mmp: append CONFIG_MACH_MMP2_DT
  ARM: mmp: fix build issue on mmp with device tree
  ARM: ux500: Enable PRCMU Timer 4 (clocksource) for Device Tree
  ARM: ux500: Disable SMSC911x platform code registration when DT is enabled
  ARM: ux500: Fork cpu-db8500 platform_devs for sequential DT enablement
  ARM: ux500: Do not attempt to register non-existent i2c devices on Snowball
  ARM: SPEAr3xx: Correct keyboard data passed from DT
  ...
parents 8dca6010 396d81cd

Documentation/arm/SPEAr/overview.txt

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Original line number Diff line number Diff line
@@ -17,14 +17,14 @@ Introduction 
  SPEAr (Platform)

	- SPEAr3XX (3XX SOC series, based on ARM9)

		- SPEAr300 (SOC)

			- SPEAr300_EVB (Evaluation Board)

			- SPEAr300 Evaluation Board

		- SPEAr310 (SOC)

			- SPEAr310_EVB (Evaluation Board)

			- SPEAr310 Evaluation Board

		- SPEAr320 (SOC)

			- SPEAr320_EVB (Evaluation Board)

			- SPEAr320 Evaluation Board

	- SPEAr6XX (6XX SOC series, based on ARM9)

		- SPEAr600 (SOC)

			- SPEAr600_EVB (Evaluation Board)

			- SPEAr600 Evaluation Board

	- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)

		- SPEAr1300 (SOC)
@@ -51,10 +51,11 @@ Introduction 
  Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for

  spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine

  specific files, like spear300.c, spear310.c, spear320.c and spear600.c.

  mach-spear* also contains board specific files for each machine type.

  mach-spear* doesn't contains board specific files as they fully support

  Flattened Device Tree.





  Document Author

  ---------------



  Viresh Kumar, (c) 2010 ST Microelectronics
 
  Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics

Documentation/devicetree/bindings/arm/lpc32xx-mic.txt

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* NXP LPC32xx Main Interrupt Controller

  (MIC, including SIC1 and SIC2 secondary controllers)



Required properties:

- compatible: Should be "nxp,lpc3220-mic"

- interrupt-controller: Identifies the node as an interrupt controller.

- interrupt-parent: Empty for the interrupt controller itself

- #interrupt-cells: The number of cells to define the interrupts. Should be 2.

  The first cell is the IRQ number

  The second cell is used to specify mode:

      1 = low-to-high edge triggered

      2 = high-to-low edge triggered

      4 = active high level-sensitive

      8 = active low level-sensitive

      Default for internal sources should be set to 4 (active high).

- reg: Should contain MIC registers location and length



Examples:

	/*

	 * MIC

	 */

	mic: interrupt-controller@40008000 {

		compatible = "nxp,lpc3220-mic";

		interrupt-controller;

		interrupt-parent;

		#interrupt-cells = <2>;

		reg = <0x40008000 0xC000>;

	};



	/*

	 * ADC

	 */

	adc@40048000 {

		compatible = "nxp,lpc3220-adc";

		reg = <0x40048000 0x1000>;

		interrupt-parent = <&mic>;

		interrupts = <39 4>;

	};

Documentation/devicetree/bindings/arm/lpc32xx.txt

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NXP LPC32xx Platforms Device Tree Bindings

------------------------------------------



Boards with the NXP LPC32xx SoC shall have the following properties:



Required root node property:



compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"

Documentation/devicetree/bindings/arm/mrvl/intc.txt

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* Marvell MMP Interrupt controller



Required properties:

- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or

  "mrvl,mmp2-mux-intc"

- reg : Address and length of the register set of the interrupt controller.

  If the interrupt controller is intc, address and length means the range

  of the whold interrupt controller. If the interrupt controller is mux-intc,

  address and length means one register. Since address of mux-intc is in the

  range of intc. mux-intc is secondary interrupt controller.

- reg-names : Name of the register set of the interrupt controller. It's

  only required in mux-intc interrupt controller.

- interrupts : Should be the port interrupt shared by mux interrupts. It's

  only required in mux-intc interrupt controller.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source.

- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt

  controller.

- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge

  detection first.



Example:

	intc: interrupt-controller@d4282000 {

		compatible = "mrvl,mmp2-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0xd4282000 0x1000>;

		mrvl,intc-nr-irqs = <64>;

	};



	intcmux4@d4282150 {

		compatible = "mrvl,mmp2-mux-intc";

		interrupts = <4>;

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0x150 0x4>, <0x168 0x4>;

		reg-names = "mux status", "mux mask";

		mrvl,intc-nr-irqs = <2>;

	};

Documentation/devicetree/bindings/arm/mrvl.txt→Documentation/devicetree/bindings/arm/mrvl/mrvl.txt

+8 −0
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@@ -4,3 +4,11 @@ Marvell Platforms Device Tree Bindings 
PXA168 Aspenite Board

Required root node properties:

	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";



PXA910 DKB Board

Required root node properties:

	- compatible = "mrvl,pxa910-dkb";



MMP2 Brownstone Board

Required root node properties:

	- compatible = "mrvl,mmp2-brownstone";

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