Commit b3127855 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2015-09-28-merged' of... 

Merge tag 'drm-intel-next-2015-09-28-merged' of git://anongit.freedesktop.org/drm-intel into drm-next

drm-intel-next-2015-09-28:
- fastboot by default for some systems (Maarten Lankhorts)
- piles of workarounds for bxt and skl
- more fbc work from Paulo
- fix hdmi hotplug detection (Sonika)
- first few patches from Ville to parametrize register macros, prep work for
  typesafe mmio functions
- prep work for nv12 rotation (Tvrtko Ursulin)
- various other bugfixes and improvements all over

I have another backmerge here since things became messy and I didn't
realize you resolved some of them already (usually you complain when
there's a conflict ...).

For 4.4 I plan one more feature round after this and then that's it.
* tag 'drm-intel-next-2015-09-28-merged' of git://anongit.freedesktop.org/drm-intel: (80 commits)
  drm/i915: Update DRIVER_DATE to 20150928
  drm/i915: fix task reference leak in i915_debugfs.c
  drm/i915: Defer adding preallocated stolen objects to the VM list
  drm/i915: Remove extraneous request cancel.
  drm/i915: Enable querying offset of UV plane with intel_plane_obj_offset
  drm/i915: Support NV12 in rotated GGTT mapping
  drm/i915: Support appending to the rotated pages mapping
  drm/i915: Support planar formats in tile height calculations
  drm/i915/bxt: Update revision id for BXT C0
  drm/i915: Parametrize CSR_PROGRAM registers
  drm/i915: Parametrize DDI_BUF_TRANS registers
  drm/i915: Parametrize TV luma/chroma filter registers
  drm/i915: Replace raw numbers with the approproate register name in ILK turbo code
  drm/i915: Parametrize ILK turbo registers
  drm/i915: Parametrize FBC_TAG registers
  drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
  drm/i915: Parametrize LRC registers
  drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc, i2c}_bus()
  drm/i915: Ignore "digital output" and "not HDMI output" bits for eDP detection
  drm/i915: Make sure we don't detect eDP on g4x
  ...
parents aa1b36f2 44cc6c08

drivers/gpu/drm/i915/i915_debugfs.c

+10 −6
Original line number Diff line number Diff line
@@ -2069,8 +2069,8 @@ static int i915_execlists(struct seq_file *m, void *data) 


		seq_printf(m, "%s\n", ring->name);



		status = I915_READ(RING_EXECLIST_STATUS(ring));

		ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);

		status = I915_READ(RING_EXECLIST_STATUS_LO(ring));

		ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));

		seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",

			   status, ctx_id);
@@ -2085,8 +2085,8 @@ static int i915_execlists(struct seq_file *m, void *data) 
			   read_pointer, write_pointer);



		for (i = 0; i < 6; i++) {

			status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);

			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);

			status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));

			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));



			seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",

				   i, status, ctx_id);
@@ -2288,9 +2288,13 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) 


	list_for_each_entry_reverse(file, &dev->filelist, lhead) {

		struct drm_i915_file_private *file_priv = file->driver_priv;

		struct task_struct *task;



		seq_printf(m, "\nproc: %s\n",

			   get_pid_task(file->pid, PIDTYPE_PID)->comm);

		task = get_pid_task(file->pid, PIDTYPE_PID);

		if (!task)

			return -ESRCH;

		seq_printf(m, "\nproc: %s\n", task->comm);

		put_task_struct(task);

		idr_for_each(&file_priv->context_idr, per_file_ctx,

			     (void *)(unsigned long)m);

	}

drivers/gpu/drm/i915/i915_dma.c

+4 −11
Original line number Diff line number Diff line
@@ -631,17 +631,6 @@ static void gen9_sseu_info_init(struct drm_device *dev) 
	u32 fuse2, s_enable, ss_disable, eu_disable;

	u8 eu_mask = 0xff;



	/*

	 * BXT has a single slice. BXT also has at most 6 EU per subslice,

	 * and therefore only the lowest 6 bits of the 8-bit EU disable

	 * fields are valid.

	*/

	if (IS_BROXTON(dev)) {

		s_max = 1;

		eu_max = 6;

		eu_mask = 0x3f;

	}



	info = (struct intel_device_info *)&dev_priv->info;

	fuse2 = I915_READ(GEN8_FUSE2);

	s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
@@ -1137,6 +1126,10 @@ int i915_driver_unload(struct drm_device *dev) 
		dev_priv->vbt.child_dev = NULL;

		dev_priv->vbt.child_dev_num = 0;

	}

	kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);

	dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;

	kfree(dev_priv->vbt.lfp_lvds_vbt_mode);

	dev_priv->vbt.lfp_lvds_vbt_mode = NULL;



	vga_switcheroo_unregister_client(dev->pdev);

	vga_client_register(dev->pdev, NULL, NULL, NULL);

drivers/gpu/drm/i915/i915_drv.c

+4 −4
Original line number Diff line number Diff line
@@ -1120,7 +1120,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);



	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)

		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);

		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));



	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);

	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
@@ -1164,7 +1164,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 
	s->pm_ier		= I915_READ(GEN6_PMIER);



	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)

		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);

		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));



	/* GT SA CZ domain, 0x100000-0x138124 */

	s->tilectl		= I915_READ(TILECTL);
@@ -1202,7 +1202,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);



	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)

		I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);

		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);



	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);

	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
@@ -1246,7 +1246,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN6_PMIER,		s->pm_ier);



	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)

		I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);

		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);



	/* GT SA CZ domain, 0x100000-0x138124 */

	I915_WRITE(TILECTL,			s->tilectl);

drivers/gpu/drm/i915/i915_drv.h

+26 −14
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20150911"

#define DRIVER_DATE		"20150928"



#undef WARN_ON

/* Many gcc seem to no see through this and fall over :( */
@@ -890,7 +890,6 @@ struct intel_context { 
	} legacy_hw_ctx;



	/* Execlists */

	bool rcs_initialized;

	struct {

		struct drm_i915_gem_object *state;

		struct intel_ringbuffer *ringbuf;
@@ -949,6 +948,9 @@ struct i915_fbc { 
		FBC_CHIP_DEFAULT, /* disabled by default on this chip */

		FBC_ROTATION, /* rotation is not supported */

		FBC_IN_DBG_MASTER, /* kernel debugger is active */

		FBC_BAD_STRIDE, /* stride is not supported */

		FBC_PIXEL_RATE, /* pixel rate is too big */

		FBC_PIXEL_FORMAT /* pixel format is invalid */

	} no_fbc_reason;



	bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
@@ -2015,25 +2017,26 @@ struct drm_i915_gem_object_ops { 


/*

 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is

 * considered to be the frontbuffer for the given plane interface-vise. This

 * considered to be the frontbuffer for the given plane interface-wise. This

 * doesn't mean that the hw necessarily already scans it out, but that any

 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.

 *

 * We have one bit per pipe and per scanout plane type.

 */

#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4

#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5

#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8

#define INTEL_FRONTBUFFER_BITS \

	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)

#define INTEL_FRONTBUFFER_PRIMARY(pipe) \

	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))

#define INTEL_FRONTBUFFER_CURSOR(pipe) \

	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))

#define INTEL_FRONTBUFFER_SPRITE(pipe) \

	(1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))

#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \

	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))

#define INTEL_FRONTBUFFER_OVERLAY(pipe) \

	(1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))

	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))

#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \

	(0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))

	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))



struct drm_i915_gem_object {

	struct drm_gem_object base;
@@ -2491,6 +2494,11 @@ struct drm_i915_cmd_table { 
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \

				 INTEL_DEVID(dev) == 0x1915 || \

				 INTEL_DEVID(dev) == 0x191E)

#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \

				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)

#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \

				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)



#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)



#define SKL_REVID_A0		(0x0)
@@ -2502,7 +2510,7 @@ struct drm_i915_cmd_table { 


#define BXT_REVID_A0		(0x0)

#define BXT_REVID_B0		(0x3)

#define BXT_REVID_C0		(0x6)

#define BXT_REVID_C0		(0x9)



/*

 * The genX designation typically refers to the render engine, so render
@@ -2581,7 +2589,7 @@ struct drm_i915_cmd_table { 
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)

#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))



#define HAS_CSR(dev)	(IS_SKYLAKE(dev))

#define HAS_CSR(dev)	(IS_GEN9(dev))



#define HAS_GUC_UCODE(dev)	(IS_GEN9(dev))

#define HAS_GUC_SCHED(dev)	(IS_GEN9(dev))
@@ -2647,7 +2655,6 @@ struct i915_params { 
	int enable_cmd_parser;

	/* leave bools at the end to not create holes */

	bool enable_hangcheck;

	bool fastboot;

	bool prefault_disable;

	bool load_detect_test;

	bool reset;
@@ -2738,6 +2745,9 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 


void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);

void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,

				   uint32_t mask,

				   uint32_t bits);

void

ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);

void
@@ -2805,8 +2815,6 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 
						  size_t size);

struct drm_i915_gem_object *i915_gem_object_create_from_data(

		struct drm_device *dev, const void *data, size_t size);

void i915_init_vm(struct drm_i915_private *dev_priv,

		  struct i915_address_space *vm);

void i915_gem_free_object(struct drm_gem_object *obj);

void i915_gem_vma_destroy(struct i915_vma *vma);
@@ -3173,6 +3181,10 @@ static inline void i915_gem_chipset_flush(struct drm_device *dev) 
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,

				struct drm_mm_node *node, u64 size,

				unsigned alignment);

int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,

					 struct drm_mm_node *node, u64 size,

					 unsigned alignment, u64 start,

					 u64 end);

void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,

				 struct drm_mm_node *node);

int i915_gem_init_stolen(struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+37 −38
Original line number Diff line number Diff line
@@ -1713,8 +1713,8 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 


/**

 * i915_gem_fault - fault a page into the GTT

 * vma: VMA in question

 * vmf: fault info

 * @vma: VMA in question

 * @vmf: fault info

 *

 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped

 * from userspace.  The fault handler takes care of binding the object to
@@ -4609,14 +4609,8 @@ int i915_gem_init_rings(struct drm_device *dev) 
			goto cleanup_vebox_ring;

	}



	ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));

	if (ret)

		goto cleanup_bsd2_ring;



	return 0;



cleanup_bsd2_ring:

	intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);

cleanup_vebox_ring:

	intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);

cleanup_blt_ring:
@@ -4687,6 +4681,7 @@ i915_gem_init_hw(struct drm_device *dev) 
	}



	/* We can't enable contexts until all firmware is loaded */

	if (HAS_GUC_UCODE(dev)) {

		ret = intel_guc_ucode_load(dev);

		if (ret) {

			/*
@@ -4696,11 +4691,21 @@ i915_gem_init_hw(struct drm_device *dev) 
			 * discard the error and carry on.

			 */

			DRM_ERROR("Failed to initialize GuC, error %d%s\n", ret,

			i915.enable_guc_submission ? "" : " (ignored)");

				  i915.enable_guc_submission ? "" :

				  " (ignored)");

			ret = i915.enable_guc_submission ? -EIO : 0;

			if (ret)

				goto out;

		}

	}



	/*

	 * Increment the next seqno by 0x100 so we have a visible break

	 * on re-initialisation

	 */

	ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);

	if (ret)

		goto out;



	/* Now it is safe to go back round and do everything else: */

	for_each_ring(ring, dev_priv, i) {
@@ -4839,18 +4844,6 @@ init_ring_lists(struct intel_engine_cs *ring) 
	INIT_LIST_HEAD(&ring->request_list);

}



void i915_init_vm(struct drm_i915_private *dev_priv,

		  struct i915_address_space *vm)

{

	if (!i915_is_ggtt(vm))

		drm_mm_init(&vm->mm, vm->start, vm->total);

	vm->dev = dev_priv->dev;

	INIT_LIST_HEAD(&vm->active_list);

	INIT_LIST_HEAD(&vm->inactive_list);

	INIT_LIST_HEAD(&vm->global_link);

	list_add_tail(&vm->global_link, &dev_priv->vm_list);

}



void

i915_gem_load(struct drm_device *dev)

{
@@ -4874,8 +4867,6 @@ i915_gem_load(struct drm_device *dev) 
				  NULL);



	INIT_LIST_HEAD(&dev_priv->vm_list);

	i915_init_vm(dev_priv, &dev_priv->gtt.base);



	INIT_LIST_HEAD(&dev_priv->context_list);

	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);

	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
@@ -4903,6 +4894,14 @@ i915_gem_load(struct drm_device *dev) 
		dev_priv->num_fence_regs =

				I915_READ(vgtif_reg(avail_rs.fence_num));



	/*

	 * Set initial sequence number for requests.

	 * Using this number allows the wraparound to happen early,

	 * catching any obvious problems.

	 */

	dev_priv->next_seqno = ((u32)~0 - 0x1100);

	dev_priv->last_seqno = ((u32)~0 - 0x1101);



	/* Initialize fence registers to zero */

	INIT_LIST_HEAD(&dev_priv->mm.fence_list);

	i915_gem_restore_fences(dev);
@@ -4972,9 +4971,9 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file) 


/**

 * i915_gem_track_fb - update frontbuffer tracking

 * old: current GEM buffer for the frontbuffer slots

 * new: new GEM buffer for the frontbuffer slots

 * frontbuffer_bits: bitmask of frontbuffer slots

 * @old: current GEM buffer for the frontbuffer slots

 * @new: new GEM buffer for the frontbuffer slots

 * @frontbuffer_bits: bitmask of frontbuffer slots

 *

 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them

 * from @old and setting them in @new. Both @old and @new can be NULL.

CRA Git | Maintained and supported by SUSTech CRA and CCSE