Commit b2f874d2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-5.3-201906210814' of... 

Merge tag 'sunxi-clk-for-5.3-201906210814' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

 - A few patches to fix two minor bugs
 - Introduce a schema for our device tree bindings

* tag 'sunxi-clk-for-5.3-201906210814' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  dt-bindings: clk: Convert Allwinner CCU to a schema
  clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
  clk-sunxi: fix a missing-check bug in sunxi_divs_clk_setup()
parents a188339c b467ec06

Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-ccu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner Clock Control Unit Device Tree Bindings



maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <maxime.ripard@bootlin.com>



properties:

  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  compatible:

    enum:

      - allwinner,sun4i-a10-ccu

      - allwinner,sun5i-a10s-ccu

      - allwinner,sun5i-a13-ccu

      - allwinner,sun6i-a31-ccu

      - allwinner,sun7i-a20-ccu

      - allwinner,sun8i-a23-ccu

      - allwinner,sun8i-a33-ccu

      - allwinner,sun8i-a83t-ccu

      - allwinner,sun8i-a83t-r-ccu

      - allwinner,sun8i-h3-ccu

      - allwinner,sun8i-h3-r-ccu

      - allwinner,sun8i-r40-ccu

      - allwinner,sun8i-v3s-ccu

      - allwinner,sun9i-a80-ccu

      - allwinner,sun50i-a64-ccu

      - allwinner,sun50i-a64-r-ccu

      - allwinner,sun50i-h5-ccu

      - allwinner,sun50i-h6-ccu

      - allwinner,sun50i-h6-r-ccu

      - allwinner,suniv-f1c100s-ccu

      - nextthing,gr8-ccu



  reg:

    maxItems: 1



  clocks:

    minItems: 2

    maxItems: 4

    items:

      - description: High Frequency Oscillator (usually at 24MHz)

      - description: Low Frequency Oscillator (usually at 32kHz)

      - description: Internal Oscillator

      - description: Peripherals PLL



  clock-names:

    minItems: 2

    maxItems: 4

    items:

      - const: hosc

      - const: losc

      - const: iosc

      - const: pll-periph



required:

  - "#clock-cells"

  - "#reset-cells"

  - compatible

  - reg

  - clocks

  - clock-names



if:

  properties:

    compatible:

      enum:

        - allwinner,sun8i-a83t-r-ccu

        - allwinner,sun8i-h3-r-ccu

        - allwinner,sun50i-a64-r-ccu

        - allwinner,sun50i-h6-r-ccu



then:

  properties:

    clocks:

      minItems: 4

      maxItems: 4



    clock-names:

      minItems: 4

      maxItems: 4



else:

  if:

    properties:

      compatible:

        const: allwinner,sun50i-h6-ccu



  then:

    properties:

      clocks:

        minItems: 3

        maxItems: 3



      clock-names:

        minItems: 3

        maxItems: 3



  else:

    properties:

      clocks:

        minItems: 2

        maxItems: 2



      clock-names:

        minItems: 2

        maxItems: 2



additionalProperties: false



examples:

  - |

    ccu: clock@1c20000 {

        compatible = "allwinner,sun8i-h3-ccu";

        reg = <0x01c20000 0x400>;

        clocks = <&osc24M>, <&osc32k>;

        clock-names = "hosc", "losc";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };



  - |

    r_ccu: clock@1f01400 {

        compatible = "allwinner,sun50i-a64-r-ccu";

        reg = <0x01f01400 0x100>;

        clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu 11>;

        clock-names = "hosc", "losc", "iosc", "pll-periph";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

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Allwinner Clock Control Unit Binding

------------------------------------



Required properties :

- compatible: must contain one of the following compatibles:

		- "allwinner,sun4i-a10-ccu"

		- "allwinner,sun5i-a10s-ccu"

		- "allwinner,sun5i-a13-ccu"

		- "allwinner,sun6i-a31-ccu"

		- "allwinner,sun7i-a20-ccu"

		- "allwinner,sun8i-a23-ccu"

		- "allwinner,sun8i-a33-ccu"

		- "allwinner,sun8i-a83t-ccu"

		- "allwinner,sun8i-a83t-r-ccu"

		- "allwinner,sun8i-h3-ccu"

		- "allwinner,sun8i-h3-r-ccu"

+		- "allwinner,sun8i-r40-ccu"

		- "allwinner,sun8i-v3s-ccu"

		- "allwinner,sun9i-a80-ccu"

		- "allwinner,sun50i-a64-ccu"

		- "allwinner,sun50i-a64-r-ccu"

		- "allwinner,sun50i-h5-ccu"

		- "allwinner,sun50i-h6-ccu"

		- "allwinner,sun50i-h6-r-ccu"

		- "allwinner,suniv-f1c100s-ccu"

		- "nextthing,gr8-ccu"



- reg: Must contain the registers base address and length

- clocks: phandle to the oscillators feeding the CCU. Two are needed:

  - "hosc": the high frequency oscillator (usually at 24MHz)

  - "losc": the low frequency oscillator (usually at 32kHz)

	    On the A83T, this is the internal 16MHz oscillator divided by 512

- clock-names: Must contain the clock names described just above

- #clock-cells : must contain 1

- #reset-cells : must contain 1



For the main CCU on H6, one more clock is needed:

- "iosc": the SoC's internal frequency oscillator



For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:

- "pll-periph": the SoC's peripheral PLL from the main CCU

- "iosc": the SoC's internal frequency oscillator



Example for generic CCU:

ccu: clock@1c20000 {

	compatible = "allwinner,sun8i-h3-ccu";

	reg = <0x01c20000 0x400>;

	clocks = <&osc24M>, <&osc32k>;

	clock-names = "hosc", "losc";

	#clock-cells = <1>;

	#reset-cells = <1>;

};



Example for PRCM CCU:

r_ccu: clock@1f01400 {

	compatible = "allwinner,sun50i-a64-r-ccu";

	reg = <0x01f01400 0x100>;

	clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;

	clock-names = "hosc", "losc", "iosc", "pll-periph";

	#clock-cells = <1>;

	#reset-cells = <1>;

};

drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

+1 −1
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@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2", 
static SUNXI_CCU_GATE(r_apb1_ir_clk,	"r-apb1-ir",	"r-apb1",

		      0x1cc, BIT(0), 0);

static SUNXI_CCU_GATE(r_apb1_w1_clk,	"r-apb1-w1",	"r-apb1",

		      0x1cc, BIT(0), 0);

		      0x1ec, BIT(0), 0);



/* Information of IR(RX) mod clock is gathered from BSP source code */

static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };

drivers/clk/sunxi/clk-sunxi.c

+2 −0
Original line number Diff line number Diff line
@@ -989,6 +989,8 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node, 
		if (endp) {

			derived_name = kstrndup(clk_name, endp - clk_name,

						GFP_KERNEL);

			if (!derived_name)

				return NULL;

			factors.name = derived_name;

		} else {

			factors.name = clk_name;

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