Commit b2edcfc8 authored by Huacai Chen's avatar Huacai Chen Committed by Ralf Baechle
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MIPS: Loongson: Add Loongson-3A R2 basic support 



Loongson-3 CPU family:

Code-name       Brand-name       PRId
Loongson-3A R1  Loongson-3A1000  0x6305
Loongson-3A R2  Loongson-3A2000  0x6308
Loongson-3B R1  Loongson-3B1000  0x6306
Loongson-3B R2  Loongson-3B1500  0x6307

Features of R2 revision of Loongson-3A:

  - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache).
  - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is
     64 bytes.
  - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way
     set-associative).
  - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/
     Execute-Inhibit.

[ralf@linux-mips.org: Resolved merge conflicts.]

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12751/
Patchwork: https://patchwork.linux-mips.org/patch/13136/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 24653515

arch/mips/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -1354,6 +1354,7 @@ config CPU_LOONGSON3 
	select CPU_SUPPORTS_HUGEPAGES

	select WEAK_ORDERING

	select WEAK_REORDERING_BEYOND_LLSC

	select MIPS_PGD_C0_CONTEXT

	select ARCH_REQUIRE_GPIOLIB

	help

		The Loongson 3 processor implements the MIPS64R2 instruction
@@ -1823,6 +1824,7 @@ config CPU_BMIPS5000 
config SYS_HAS_CPU_LOONGSON3

	bool

	select CPU_SUPPORTS_CPUFREQ

	select CPU_HAS_RIXI



config SYS_HAS_CPU_LOONGSON2E

	bool

arch/mips/include/asm/cacheops.h

+6 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define Cache_I				0x00

#define Cache_D				0x01

#define Cache_T				0x02

#define Cache_V				0x02 /* Loongson-3 */

#define Cache_S				0x03



#define Index_Writeback_Inv		0x00
@@ -107,4 +108,9 @@ 
 */

#define Hit_Invalidate_I_Loongson2	(Cache_I | 0x00)



/*

 * Loongson3-specific cacheops

 */

#define Index_Writeback_Inv_V		(Cache_V | Index_Writeback_Inv)



#endif	/* __ASM_CACHEOPS_H */

arch/mips/include/asm/cpu-info.h

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ struct cpuinfo_mips { 
	int			tlbsizeftlbways;

	struct cache_desc	icache; /* Primary I-cache */

	struct cache_desc	dcache; /* Primary D or combined I/D cache */

	struct cache_desc	vcache; /* Victim cache, between pcache and scache */

	struct cache_desc	scache; /* Secondary cache */

	struct cache_desc	tcache; /* Tertiary/split secondary cache */

	int			srsets; /* Shadow register sets */

arch/mips/include/asm/cpu.h

+3 −1
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ 
#define PRID_COMP_LEXRA		0x0b0000

#define PRID_COMP_NETLOGIC	0x0c0000

#define PRID_COMP_CAVIUM	0x0d0000

#define PRID_COMP_LOONGSON	0x140000

#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750 */

#define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775 */

#define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
@@ -241,9 +242,10 @@ 
#define PRID_REV_LOONGSON1B	0x0020

#define PRID_REV_LOONGSON2E	0x0002

#define PRID_REV_LOONGSON2F	0x0003

#define PRID_REV_LOONGSON3A	0x0005

#define PRID_REV_LOONGSON3A_R1	0x0005

#define PRID_REV_LOONGSON3B_R1	0x0006

#define PRID_REV_LOONGSON3B_R2	0x0007

#define PRID_REV_LOONGSON3A_R2	0x0008



/*

 * Older processors used to encode processor version and revision in two

arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h

+5 −13
Original line number Diff line number Diff line
@@ -16,11 +16,6 @@ 
#ifndef __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H

#define __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H



#define cpu_dcache_line_size()	32

#define cpu_icache_line_size()	32

#define cpu_scache_line_size()	32





#define cpu_has_32fpr		1

#define cpu_has_3k_cache	0

#define cpu_has_4k_cache	1
@@ -31,24 +26,17 @@ 
#define cpu_has_counter		1

#define cpu_has_dc_aliases	(PAGE_SIZE < 0x4000)

#define cpu_has_divec		0

#define cpu_has_dsp		0

#define cpu_has_dsp2		0

#define cpu_has_ejtag		0

#define cpu_has_ic_fills_f_dc	0

#define cpu_has_inclusive_pcaches	1

#define cpu_has_llsc		1

#define cpu_has_mcheck		0

#define cpu_has_mdmx		0

#define cpu_has_mips16		0

#define cpu_has_mips32r2	0

#define cpu_has_mips3d		0

#define cpu_has_mips64r2	0

#define cpu_has_mipsmt		0

#define cpu_has_prefetch	0

#define cpu_has_smartmips	0

#define cpu_has_tlb		1

#define cpu_has_tx39_cache	0

#define cpu_has_userlocal	0

#define cpu_has_vce		0

#define cpu_has_veic		0

#define cpu_has_vint		0
@@ -56,6 +44,10 @@ 
#define cpu_has_watch		1

#define cpu_has_local_ebase	0



#define cpu_has_wsbh		IS_ENABLED(CONFIG_CPU_LOONGSON3)

#ifdef CONFIG_CPU_LOONGSON3

#define cpu_has_wsbh		1

#define cpu_has_ic_fills_f_dc	1

#define cpu_hwrena_impl_bits	0xc0000000

#endif



#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */

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