Commit b2e6d305 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-exynos' into next 

* pci/host-exynos:
  PCI: exynos: Support the PHY generic framework
  Documentation: binding: Modify the exynos5440 PCIe binding
  phy: phy-exynos-pcie: Add support for Exynos PCIe PHY
  Documentation: samsung-phy: Add exynos-pcie-phy binding
  PCI: exynos: Refactor to make it easier to support other SoCs
  PCI: exynos: Remove duplicated code
  PCI: exynos: Use the bitops BIT() macro to build bitmasks
  PCI: exynos: Remove unnecessary local variables
  PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
  PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"

Conflicts:
	drivers/pci/dwc/pci-exynos.c
parents 1a557613 e7cd7ef5

Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt

+29 −0
Original line number Diff line number Diff line
@@ -7,8 +7,19 @@ Required properties: 
- compatible: "samsung,exynos5440-pcie"

- reg: base addresses and lengths of the pcie controller,

	the phy controller, additional register for the phy controller.

	(Registers for the phy controller are DEPRECATED.

	 Use the PHY framework.)

- reg-names : First name should be set to "elbi".

	And use the "config" instead of getting the confgiruation address space

	from "ranges".

	NOTE: When use the "config" property, reg-names must be set.

- interrupts: A list of interrupt outputs for level interrupt,

	pulse interrupt, special interrupt.

- phys: From PHY binding. Phandle for the Generic PHY.

	Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt



Other common properties refer to

	Documentation/devicetree/binding/pci/designware-pcie.txt



Example:
@@ -54,6 +65,24 @@ SoC specific DT Entry: 
		num-lanes = <4>;

	};



With using PHY framework:

	pcie_phy0: pcie-phy@270000 {

		...

		reg = <0x270000 0x1000>, <0x271000 0x40>;

		reg-names = "phy", "block";

		...

	};



	pcie@290000 {

		...

		reg = <0x290000 0x1000>, <0x40000000 0x1000>;

		reg-names = "elbi", "config";

		phys = <&pcie_phy0>;

		ranges = <0x81000000 0 0	  0x60001000 0 0x00010000

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;

		...

	};



Board specific DT Entry:



	pcie@290000 {

Documentation/devicetree/bindings/phy/samsung-phy.txt

+17 −0
Original line number Diff line number Diff line
@@ -191,3 +191,20 @@ Example: 
		usbdrdphy0 = &usb3_phy0;

		usbdrdphy1 = &usb3_phy1;

	};



Samsung Exynos SoC series PCIe PHY controller

--------------------------------------------------

Required properties:

- compatible : Should be set to "samsung,exynos5440-pcie-phy"

- #phy-cells : Must be zero

- reg : a register used by phy driver.

	- First is for phy register, second is for block register.

- reg-names : Must be set to "phy" and "block".



Example:

	pcie_phy0: pcie-phy@270000 {

		#phy-cells = <0>;

		compatible = "samsung,exynos5440-pcie-phy";

		reg = <0x270000 0x1000>, <0x271000 0x40>;

		reg-names = "phy", "block";

	};

drivers/pci/dwc/pci-exynos.c

+333 −226

File changed.

Preview size limit exceeded, changes collapsed.

drivers/phy/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -331,6 +331,14 @@ config PHY_EXYNOS5_USBDRD 
	  This driver provides PHY interface for USB 3.0 DRD controller

	  present on Exynos5 SoC series.



config PHY_EXYNOS_PCIE

	bool "Exynos PCIe PHY driver"

	depends on OF && (ARCH_EXYNOS || COMPILE_TEST)

	select GENERIC_PHY

	help

	  Enable PCIe PHY support for Exynos SoC series.

	  This driver provides PHY interface for Exynos PCIe controller.



config PHY_PISTACHIO_USB

	tristate "IMG Pistachio USB2.0 PHY driver"

	depends on MACH_PISTACHIO

drivers/phy/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o 
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o

phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o

obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o

obj-$(CONFIG_PHY_EXYNOS_PCIE)	+= phy-exynos-pcie.o

obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o

obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o

obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o

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