Commit b2e3c431 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC driver updates from Arnd Bergmann:
 "Driver updates for ARM SoCs.

  A handful of driver changes this time around. The larger changes are:

   - Reset drivers for hi3660 and zx2967

   - AHCI driver for Davinci, acked by Tejun and brought in here due to
     platform dependencies

   - Cleanups of atmel-ebi (External Bus Interface)

   - Tweaks for Rockchip GRF (General Register File) usage (kitchensink
     misc register range on the SoCs)

   - PM domains changes for support of two new ZTE SoCs (zx296718 and
     zx2967)"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
  soc: samsung: pmu: Add register defines for pad retention control
  reset: make zx2967 explicitly non-modular
  reset: core: fix reset_control_put
  soc: samsung: pm_domains: Read domain name from the new label property
  soc: samsung: pm_domains: Remove message about failed memory allocation
  soc: samsung: pm_domains: Remove unused name field
  soc: samsung: pm_domains: Use full names in subdomains registration log
  sata: ahci-da850: un-hardcode the MPY bits
  sata: ahci-da850: add a workaround for controller instability
  sata: ahci: export ahci_do_hardreset() locally
  sata: ahci-da850: implement a workaround for the softreset quirk
  sata: ahci-da850: add device tree match table
  sata: ahci-da850: get the sata clock using a connection id
  soc: samsung: pmu: Remove duplicated define for ARM_L2_OPTION register
  memory: atmel-ebi: Enable the SMC clock if specified
  soc: samsung: pmu: Remove unused and duplicated defines
  memory: atmel-ebi: Properly handle multiple reference to the same CS
  memory: atmel-ebi: Fix the test to enable generic SMC logic
  soc: samsung: pm_domains: Add new Exynos5433 compatible
  soc: samsung: pmu: Add dummy support for Exynos5433 SoC
  ...
parents c61c15e0 db27dd05

Documentation/devicetree/bindings/power/pd-samsung.txt

+5 −0
Original line number Diff line number Diff line
@@ -6,12 +6,15 @@ to gate power to one or more peripherals on the processor. 
Required Properties:

- compatible: should be one of the following.

    * samsung,exynos4210-pd - for exynos4210 type power domain.

    * samsung,exynos5433-pd - for exynos5433 type power domain.

- reg: physical base address of the controller and length of memory mapped

    region.

- #power-domain-cells: number of cells in power domain specifier;

    must be 0.



Optional Properties:

- label: Human readable string with domain name. Will be visible in userspace

	to let user to distinguish between multiple domains in SoC.

- clocks: List of clock handles. The parent clocks of the input clocks to the

	devices in this power domain are set to oscclk before power gating

	and restored back after powering on a domain. This is required for
@@ -38,6 +41,7 @@ Example: 
		compatible = "samsung,exynos4210-pd";

		reg = <0x10023C00 0x10>;

		#power-domain-cells = <0>;

		label = "LCD0";

	};



	mfc_pd: power-domain@10044060 {
@@ -46,6 +50,7 @@ Example: 
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;

		clock-names = "oscclk", "clk0";

		#power-domain-cells = <0>;

		label = "MFC";

	};



See Documentation/devicetree/bindings/power/power_domain.txt for description

Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt

0 → 100644
+43 −0
Original line number Diff line number Diff line 
Hisilicon System Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



The reset controller registers are part of the system-ctl block on

hi3660 SoC.



Required properties:

- compatible: should be

		 "hisilicon,hi3660-reset"

- hisi,rst-syscon: phandle of the reset's syscon.

- #reset-cells : Specifies the number of cells needed to encode a

  reset source.  The type shall be a <u32> and the value shall be 2.



	 Cell #1 : offset of the reset assert control

	           register from the syscon register base

		   offset + 4: deassert control register

		   offset + 8: status control register

	 Cell #2 : bit position of the reset in the reset control register



Example:

	iomcu: iomcu@ffd7e000 {

		compatible = "hisilicon,hi3660-iomcu", "syscon";

		reg = <0x0 0xffd7e000 0x0 0x1000>;

	};



	iomcu_rst: iomcu_rst_controller {

		compatible = "hisilicon,hi3660-reset";

		hisi,rst-syscon = <&iomcu>;

		#reset-cells = <2>;

	};



Specifying reset lines connected to IP modules

==============================================

example:



        i2c0: i2c@..... {

                ...

		resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */

                ...

        };

Documentation/devicetree/bindings/reset/ti-syscon-reset.txt

+4 −4
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ Example: 
--------

The following example demonstrates a syscon node, the reset controller node

using the syscon node, and a consumer (a DSP device) on the TI Keystone 2

Edison SoC.

66AK2E SoC.



/ {

	soc {
@@ -71,13 +71,13 @@ Edison SoC. 
			compatible = "syscon", "simple-mfd";

			reg = <0x02350000 0x1000>;



			pscrst: psc-reset {

			pscrst: reset-controller {

				compatible = "ti,k2e-pscrst", "ti,syscon-reset";

				#reset-cells = <1>;



				ti,reset-bits = <

					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET)   /* 0: pcrst-dsp0 */

					0xa40 5 0xa44 3 0     0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE)  /* 1: pcrst-example */

					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET   | STATUS_CLEAR) /* 0: dsp0 */

					0xa40 5 0xa44 3 0     0 (ASSERT_SET   | DEASSERT_CLEAR | STATUS_NONE)  /* 1: example */

				>;

			};

		};

Documentation/devicetree/bindings/reset/uniphier-reset.txt

+24 −23
Original line number Diff line number Diff line
@@ -6,14 +6,14 @@ System reset 


Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-reset" - for sLD3 SoC.

    "socionext,uniphier-ld4-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-reset" - for Pro5 SoC.

    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-reset" - for LD20 SoC.

    "socionext,uniphier-sld3-reset" - for sLD3 SoC

    "socionext,uniphier-ld4-reset"  - for LD4 SoC

    "socionext,uniphier-pro4-reset" - for Pro4 SoC

    "socionext,uniphier-sld8-reset" - for sLD8 SoC

    "socionext,uniphier-pro5-reset" - for Pro5 SoC

    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-reset" - for LD11 SoC

    "socionext,uniphier-ld20-reset" - for LD20 SoC

- #reset-cells: should be 1.



Example:
@@ -37,14 +37,15 @@ Media I/O (MIO) reset, SD reset 


Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.

    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC.

    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC.

    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC

    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC

    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC

    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC

    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC

    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)

    "socionext,uniphier-ld11-sd-reset"  - for LD11 SoC (SD)

    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC

- #reset-cells: should be 1.



Example:
@@ -68,13 +69,13 @@ Peripheral reset 


Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.

    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC.

    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC

    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC

    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC

    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC

    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC

    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC

- #reset-cells: should be 1.



Example:

Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt

0 → 100644
+20 −0
Original line number Diff line number Diff line 
ZTE zx2967 SoCs Reset Controller

=======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: should be one of the following.

	* zte,zx296718-reset

- reg: physical base address of the controller and length of memory mapped

	region.

- #reset-cells: must be 1.



example:



	reset: reset-controller@1461060 {

		compatible = "zte,zx296718-reset";

		reg = <0x01461060 0x8>;

		#reset-cells = <1>;

	};

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