ARM: dts: STi: Add fake reg property for miphy28lp_phy (b2d81762) · Commits · 戴 / test

Add fake reg property to miphy28lp_phy. This allows to fix the following warning when compiling dtb with W=1 option: arch/arm/boot/dts/stih407-b2120.dtb: Warning (simple_bus_reg): Node /soc/miphy28lp missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg): Node /soc/miphy28lp missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg): Node /soc/miphy28lp missing or empty reg/ranges property arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg): Node /soc/miphy28lp missing or empty reg/ranges property Signed-off-by:

Patrice Chotard <patrice.chotard@st.com>

arch/arm/boot/dts/stih407-family.dtsi

+2 −1

Original line number	Diff line number	Diff line
		@@ -389,12 +389,13 @@
		reset-names = "global", "port";
		};

		miphy28lp_phy: miphy28lp {
		miphy28lp_phy: miphy28lp@0 {
		compatible = "st,miphy28lp-phy";
		st,syscfg = <&syscfg_core>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		reg = <0 0>;

		phy_port0: port@9b22000 {
		reg = <0x9b22000 0xff>,

arch/arm/boot/dts/stih410-b2260.dts

+1 −1

Original line number	Diff line number	Diff line
		@@ -200,7 +200,7 @@
		};
		};

		miphy28lp_phy: miphy28lp {
		miphy28lp_phy: miphy28lp@0 {

		phy_port1: port@9b2a000 {
		st,osc-force-ext;

arch/arm/boot/dts/stih418-b2199.dts

+1 −1

Original line number	Diff line number	Diff line
		@@ -88,7 +88,7 @@
		non-removable;
		};

		miphy28lp_phy: miphy28lp {
		miphy28lp_phy: miphy28lp@0 {

		phy_port0: port@9b22000 {
		st,osc-rdy;

arch/arm/boot/dts/stihxxx-b2120.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -80,7 +80,7 @@
		st,i2c-min-sda-pulse-width-us = <5>;
		};

		miphy28lp_phy: miphy28lp {
		miphy28lp_phy: miphy28lp@0 {

		phy_port0: port@9b22000 {
		st,osc-rdy;

Admin message