irqchip/gic-v4: Use Inner-Shareable attributes for virtual pending tables (b2cb11f4) · Commits · 戴 / test

There is no special reason to set virtual LPI pending table as non-shareable. If we choose to hard code the shareability without probing, Inner-Shareable is likely to be a better choice, as the VPEs can move around and benefit from having the redistributors snooping each other's cache, if that's something they can do. Furthermore, Hisilicon hip08 ends up with unspecified errors when mixing shareability attributes. So let's move to IS attributes for the VPT. This has also been tested on D05 and didn't show any regression. Signed-off-by:

Heyi Guo <guoheyi@huawei.com> [maz: rewrote commit message] Signed-off-by:

Marc Zyngier <maz@kernel.org> Tested-by:

Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20191130073849.38378-1-guoheyi@huawei.com

drivers/irqchip/irq-gic-v3-its.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -3560,7 +3560,7 @@ static void its_vpe_schedule(struct its_vpe *vpe)
		val = virt_to_phys(page_address(vpe->vpt_page)) &
		GENMASK_ULL(51, 16);
		val \|= GICR_VPENDBASER_RaWaWb;
		val \|= GICR_VPENDBASER_NonShareable;
		val \|= GICR_VPENDBASER_InnerShareable;
		/*
		* There is no good way of finding out if the pending table is
		* empty as we can race against the doorbell interrupt very

include/linux/irqchip/arm-gic-v3.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -320,6 +320,9 @@
		#define GICR_VPENDBASER_NonShareable \
		GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)

		#define GICR_VPENDBASER_InnerShareable \
		GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable)

		#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
		#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
		#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)

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