Commit b255e126 authored by Jianxin Pan's avatar Jianxin Pan Committed by Kevin Hilman
Browse files

arm64: dts: add support for A1 based Amlogic AD401 



Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.

Signed-off-by: default avatarJianxin Pan <jianxin.pan@amlogic.com>
Reviewed-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 46e72313

arch/arm64/boot/dts/amlogic/Makefile

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Original line number Diff line number Diff line
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb 
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb

arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts

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+30 −0
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.

 */



/dts-v1/;



#include "meson-a1.dtsi"



/ {

	compatible = "amlogic,ad401", "amlogic,a1";

	model = "Amlogic Meson A1 AD401 Development Board";



	aliases {

		serial0 = &uart_AO_B;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x0 0x0 0x8000000>;

	};

};



&uart_AO_B {

	status = "okay";

};

arch/arm64/boot/dts/amlogic/meson-a1.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "amlogic,a1";



	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0x0 0x1>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};



		l2: l2-cache0 {

			compatible = "cache";

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		linux,cma {

			compatible = "shared-dma-pool";

			reusable;

			size = <0x0 0x800000>;

			alignment = <0x0 0x400000>;

			linux,cma-default;

		};

	};



	sm: secure-monitor {

		compatible = "amlogic,meson-gxbb-sm";

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		apb: bus@fe000000 {

			compatible = "simple-bus";

			reg = <0x0 0xfe000000 0x0 0x1000000>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;



			uart_AO: serial@1c00 {

				compatible = "amlogic,meson-gx-uart",

					     "amlogic,meson-ao-uart";

				reg = <0x0 0x1c00 0x0 0x18>;

				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>, <&xtal>, <&xtal>;

				clock-names = "xtal", "pclk", "baud";

				status = "disabled";

			};



			uart_AO_B: serial@2000 {

				compatible = "amlogic,meson-gx-uart",

					     "amlogic,meson-ao-uart";

				reg = <0x0 0x2000 0x0 0x18>;

				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>, <&xtal>, <&xtal>;

				clock-names = "xtal", "pclk", "baud";

				status = "disabled";

			};

		};



		gic: interrupt-controller@ff901000 {

			compatible = "arm,gic-400";

			reg = <0x0 0xff901000 0x0 0x1000>,

			      <0x0 0xff902000 0x0 0x2000>,

			      <0x0 0xff904000 0x0 0x2000>,

			      <0x0 0xff906000 0x0 0x2000>;

			interrupt-controller;

			interrupts = <GIC_PPI 9

				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

			#interrupt-cells = <3>;

			#address-cells = <0>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};

};

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