Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

NXP i.MX System Controller Firmware (SCFW)

--------------------------------------------------------------------

The System Controller Firmware (SCFW) is a low-level system function

which runs on a dedicated Cortex-M core to provide power, clock, and

resource management. It exists on some i.MX8 processors. e.g. i.MX8QM

(QM, QP), and i.MX8QX (QXP, DX).

The AP communicates with the SC using a multi-ported MU module found

in the LSIO subsystem. The current definition of this MU module provides

5 remote AP connections to the SC to support up to 5 execution environments

(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces

with the LSIO DSC IP bus. The SC firmware will communicate with this MU

using the MSI bus.

System Controller Device Node:

============================================================

The scu node with the following properties shall be under the /firmware/ node.

Required properties:

-------------------

- compatible:	should be "fsl,imx-scu".

- mbox-names:	should include "tx0", "tx1", "tx2", "tx3",

			       "rx0", "rx1", "rx2", "rx3".

- mboxes:	List of phandle of 4 MU channels for tx and 4 MU channels

		for rx. All 8 MU channels must be in the same MU instance.

		Cross instances are not allowed. The MU instance can only

		be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need

		to make sure use the one which is not conflict with other

		execution environments. e.g. ATF.

		Note:

		Channel 0 must be "tx0" or "rx0".

		Channel 1 must be "tx1" or "rx1".

		Channel 2 must be "tx2" or "rx2".

		Channel 3 must be "tx3" or "rx3".

		e.g.

		mboxes = <&lsio_mu1 0 0

			  &lsio_mu1 0 1

			  &lsio_mu1 0 2

			  &lsio_mu1 0 3

			  &lsio_mu1 1 0

			  &lsio_mu1 1 1

			  &lsio_mu1 1 2

			  &lsio_mu1 1 3>;

		See Documentation/devicetree/bindings/mailbox/fsl,mu.txt

		for detailed mailbox binding.

i.MX SCU Client Device Node:

============================================================

Client nodes are maintained as children of the relevant IMX-SCU device node.

Power domain bindings based on SCU Message Protocol

------------------------------------------------------------

This binding for the SCU power domain providers uses the generic power

domain binding[2].

Required properties:

- compatible:		Should be "fsl,scu-pd".

- #address-cells:	Should be 1.

- #size-cells:		Should be 0.

Required properties for power domain sub nodes:

- #power-domain-cells:	Must be 0.

Optional Properties:

- reg:			Resource ID of this power domain.

			No exist means uncontrollable by user.

			See detailed Resource ID list from:

			include/dt-bindings/power/imx-rsrc.h

- power-domains:	phandle pointing to the parent power domain.

Clock bindings based on SCU Message Protocol

------------------------------------------------------------

This binding uses the common clock binding[1].

Required properties:

- compatible:		Should be "fsl,imx8qxp-clock".

- #clock-cells:		Should be 1. Contains the Clock ID value.

- clocks:		List of clock specifiers, must contain an entry for

			each required entry in clock-names

- clock-names:		Should include entries "xtal_32KHz", "xtal_24MHz"

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.

See the full list of clock IDs from:

include/dt-bindings/clock/imx8qxp-clock.h

Pinctrl bindings based on SCU Message Protocol

------------------------------------------------------------

This binding uses the i.MX common pinctrl binding[3].

Required properties:

- compatible:		Should be "fsl,imx8qxp-iomuxc".

Required properties for Pinctrl sub nodes:

- fsl,pins:		Each entry consists of 3 integers which represents

			the mux and config setting for one pin. The first 2

			integers <pin_id mux_mode> are specified using a

			PIN_FUNC_ID macro, which can be found in

			<dt-bindings/pinctrl/pads-imx8qxp.h>.

			The last integer CONFIG is the pad setting value like

			pull-up on this pin.

			Please refer to i.MX8QXP Reference Manual for detailed

			CONFIG settings.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/power/power_domain.txt

[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt

Example (imx8qxp):

-------------

lsio_mu1: mailbox@5d1c0000 {

	...

	#mbox-cells = <2>;

};

firmware {

	scu {

		compatible = "fsl,imx-scu";

		mbox-names = "tx0", "tx1", "tx2", "tx3",

			     "rx0", "rx1", "rx2", "rx3";

		mboxes = <&lsio_mu1 0 0

			  &lsio_mu1 0 1

			  &lsio_mu1 0 2

			  &lsio_mu1 0 3

			  &lsio_mu1 1 0

			  &lsio_mu1 1 1

			  &lsio_mu1 1 2

			  &lsio_mu1 1 3>;

		clk: clk {

			compatible = "fsl,imx8qxp-clk";

			#clock-cells = <1>;

		};

		iomuxc {

			compatible = "fsl,imx8qxp-iomuxc";

			pinctrl_lpuart0: lpuart0grp {

				fsl,pins = <

					SC_P_UART0_RX_ADMA_UART0_RX	0x06000020

					SC_P_UART0_TX_ADMA_UART0_TX	0x06000020

				>;

			};

			...

		};

		imx8qx-pm {

			compatible = "fsl,scu-pd";

			#address-cells = <1>;

			#size-cells = <0>;

			pd_dma: dma-power-domain {

				#power-domain-cells = <0>;

				pd_dma_lpuart0: dma-lpuart0@57 {

					reg = <SC_R_UART_0>;

					#power-domain-cells = <0>;

					power-domains = <&pd_dma>;

				};

				...

			};

			...

		};

	};

};

serial@5a060000 {

	...

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lpuart0>;

	clocks = <&clk IMX8QXP_UART0_CLK>,

		 <&clk IMX8QXP_UART0_IPG_CLK>;

	clock-names = "per", "ipg";

	power-domains = <&pd_dma_lpuart0>;

};

	debug_messages - Map the Debug message region

- reg:  register space corresponding to the debug_messages

- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot

- ti,host-id: Integer value corresponding to the host ID assigned by Firmware

	for identification of host processing entities such as virtual

	machines

Example (K2G):

-------------

	pmmc: pmmc {

		compatible = "ti,k2g-sci";

		ti,host-id = <2>;

		mbox-names = "rx", "tx";

		mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,

			<&msgmgr &msgmgr_proxy_pmmc_tx>;

- reg:

	Usage: required

	Value Type: <prop-encoded-array>

	Definition: Start address and the the size of the register region.

	Definition: The first element specifies the llcc base start address and

		    the size of the register region. The second element specifies

		    the llcc broadcast base address and size of the register region.

- reg-names:

        Usage: required

        Value Type: <stringlist>

        Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".

- interrupts:

	Usage: required

	Definition: The interrupt is associated with the llcc edac device.

			It's used for llcc cache single and double bit error detection

			and reporting.

Example:

	cache-controller@1100000 {

		compatible = "qcom,sdm845-llcc";

		reg = <0x1100000 0x250000>;

		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;

		reg-names = "llcc_base", "llcc_broadcast_base";

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

	};

Required properties:

- compatible: must contain one of the following:

 * "qcom,scm-apq8064" for APQ8064 platforms

 * "qcom,scm-msm8660" for MSM8660 platforms

 * "qcom,scm-msm8690" for MSM8690 platforms

 * "qcom,scm-msm8996" for MSM8996 platforms

 * "qcom,scm-ipq4019" for IPQ4019 platforms

 * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)

- clocks: One to three clocks may be required based on compatible.

 * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"

 * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"

 * Core, iface, and bus clocks required for "qcom,scm"

 * "qcom,scm-apq8064"

 * "qcom,scm-apq8084"

 * "qcom,scm-msm8660"

 * "qcom,scm-msm8916"

 * "qcom,scm-msm8960"

 * "qcom,scm-msm8974"

 * "qcom,scm-msm8996"

 * "qcom,scm-msm8998"

 * "qcom,scm-ipq4019"

 * "qcom,scm-sdm845"

 and:

 * "qcom,scm"

- clocks: Specifies clocks needed by the SCM interface, if any:

 * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and

   "qcom,scm-msm8960"

 * core, iface and bus clocks required for "qcom,scm-apq8084",

   "qcom,scm-msm8916" and "qcom,scm-msm8974"

- clock-names: Must contain "core" for the core clock, "iface" for the interface

  clock and "bus" for the bus clock per the requirements of the compatible.

- qcom,dload-mode: phandle to the TCSR hardware block and offset of the

	firmware {

		scm {

			compatible = "qcom,scm";

			clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;

			compatible = "qcom,msm8916", "qcom,scm";

			clocks = <&gcc GCC_CRYPTO_CLK> ,

				 <&gcc GCC_CRYPTO_AXI_CLK>,

				 <&gcc GCC_CRYPTO_AHB_CLK>;

			clock-names = "core", "bus", "iface";

		};

	};

-----------------------------------------------------------------

Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface

-----------------------------------------------------------------

The zynqmp-firmware node describes the interface to platform firmware.

ZynqMP has an interface to communicate with secure firmware. Firmware

driver provides an interface to firmware APIs. Interface APIs can be

used by any driver to communicate to PMUFW(Platform Management Unit).

These requests include clock management, pin control, device control,

power management service, FPGA service and other platform management

services.

Required properties:

 - compatible:	Must contain:	"xlnx,zynqmp-firmware"

 - method:	The method of calling the PM-API firmware layer.

		Permitted values are:

		  - "smc" : SMC #0, following the SMCCC

		  - "hvc" : HVC #0, following the SMCCC

--------------------------------------------------------------------------

Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using

Zynq MPSoC firmware interface

--------------------------------------------------------------------------

The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock

tree. It reads required input clock frequencies from the devicetree and acts

as clock provider for all clock consumers of PS clocks.

See clock_bindings.txt for more information on the generic clock bindings.

Required properties:

 - #clock-cells:	Must be 1

 - compatible:		Must contain:	"xlnx,zynqmp-clk"

 - clocks:		List of clock specifiers which are external input

			clocks to the given clock controller. Please refer

			the next section to find the input clocks for a

			given controller.

 - clock-names:		List of clock names which are exteral input clocks

			to the given clock controller. Please refer to the

			clock bindings for more details.

Input clocks for zynqmp Ultrascale+ clock controller:

The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock

inputs. These required clock inputs are:

 - pss_ref_clk (PS reference clock)

 - video_clk (reference clock for video system )

 - pss_alt_ref_clk (alternative PS reference clock)

 - aux_ref_clk

 - gt_crx_ref_clk (transceiver reference clock)

The following strings are optional parameters to the 'clock-names' property in

order to provide an optional (E)MIO clock source:

 - swdt0_ext_clk

 - swdt1_ext_clk

 - gem0_emio_clk

 - gem1_emio_clk

 - gem2_emio_clk

 - gem3_emio_clk

 - mio_clk_XX		# with XX = 00..77

 - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51

Output clocks are registered based on clock information received

from firmware. Output clocks indexes are mentioned in

include/dt-bindings/clock/xlnx,zynqmp-clk.h.

-------

Example

-------

firmware {

	zynqmp_firmware: zynqmp-firmware {

		compatible = "xlnx,zynqmp-firmware";

		method = "smc";

		zynqmp_clk: clock-controller {

			#clock-cells = <1>;

			compatible = "xlnx,zynqmp-clk";

			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;

			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";

		};

	};

};