Commit b1f6f47e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: clean up audio dto programming 



Split into DCE2/3 and DCE4/5 variants. Still todo is to
calculate the DTO dividers properly.  Add proper formula
to the comments.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 26250e65

drivers/gpu/drm/radeon/evergreen_hdmi.c

+25 −1
Original line number Diff line number Diff line
@@ -85,6 +85,30 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 
		frame[0xC] | (frame[0xD] << 8));

}



static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	u32 base_rate = 48000;



	if (!dig || !dig->afmt)

		return;



	/* XXX: properly calculate this */

	/* XXX two dtos; generally use dto0 for hdmi */

	/* Express [24MHz / target pixel clock] as an exact rational

	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);

	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);

	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));

}





/*

 * update the info frames with the data from the current display mode

 */
@@ -104,7 +128,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
		return;

	offset = dig->afmt->offset;



	r600_audio_set_clock(encoder, mode->clock);

	evergreen_audio_set_dto(encoder, mode->clock);



	WREG32(HDMI_VBI_PACKET_CONTROL + offset,

	       HDMI_NULL_SEND); /* send null packets when required */

drivers/gpu/drm/radeon/r600_audio.c

+0 −59
Original line number Diff line number Diff line
@@ -180,65 +180,6 @@ int r600_audio_init(struct radeon_device *rdev) 
	return 0;

}



/*

 * atach the audio codec to the clock source of the encoder

 */

void r600_audio_set_clock(struct drm_encoder *encoder, int clock)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	int base_rate = 48000;



	switch (radeon_encoder->encoder_id) {

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:

	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:

		WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);

		break;

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);

		break;

	default:

		dev_err(rdev->dev, "Unsupported encoder type 0x%02X\n",

			  radeon_encoder->encoder_id);

		return;

	}



	if (ASIC_IS_DCE4(rdev)) {

		/* TODO: other PLLs? */

		WREG32(EVERGREEN_AUDIO_PLL1_MUL, base_rate * 10);

		WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);

		WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);



		/* Select DTO source */

		WREG32(0x5ac, radeon_crtc->crtc_id);

	} else {

		switch (dig->dig_encoder) {

		case 0:

			WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);

			WREG32(R600_AUDIO_PLL1_DIV, clock * 100);

			WREG32(R600_AUDIO_CLK_SRCSEL, 0);

			break;



		case 1:

			WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);

			WREG32(R600_AUDIO_PLL2_DIV, clock * 100);

			WREG32(R600_AUDIO_CLK_SRCSEL, 1);

			break;

		default:

			dev_err(rdev->dev,

				"Unsupported DIG on encoder 0x%02X\n",

				radeon_encoder->encoder_id);

			return;

		}

	}

}



/*

 * release the audio timer

 * TODO: How to do this correctly on SMP systems?

drivers/gpu/drm/radeon/r600_hdmi.c

+25 −1
Original line number Diff line number Diff line
@@ -226,6 +226,30 @@ static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 
		 value, ~HDMI0_AUDIO_TEST_EN);

}



void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	u32 base_rate = 48000;



	if (!dig || !dig->afmt)

		return;



	/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.

	 * doesn't matter which one you use.  Just use the first one.

	 */

	/* XXX: properly calculate this */

	/* XXX two dtos; generally use dto0 for hdmi */

	/* Express [24MHz / target pixel clock] as an exact rational

	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);

	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);

	WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */

}



/*

 * update the info frames with the data from the current display mode
@@ -246,7 +270,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod 
		return;

	offset = dig->afmt->offset;



	r600_audio_set_clock(encoder, mode->clock);

	r600_audio_set_dto(encoder, mode->clock);



	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,

	       HDMI0_NULL_SEND); /* send null packets when required */

drivers/gpu/drm/radeon/radeon_asic.h

+0 −1
Original line number Diff line number Diff line
@@ -374,7 +374,6 @@ void r600_disable_interrupts(struct radeon_device *rdev); 
void r600_rlc_stop(struct radeon_device *rdev);

/* r600 audio */

int r600_audio_init(struct radeon_device *rdev);

void r600_audio_set_clock(struct drm_encoder *encoder, int clock);

struct r600_audio r600_audio_status(struct radeon_device *rdev);

void r600_audio_fini(struct radeon_device *rdev);

int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);

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