Commit b1f4c209 authored Apr 01, 2020 by Oleksij Rempel Committed by David S. Miller Apr 01, 2020

net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035



The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.

This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".

To reproduce this bug, configure the PHY  with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.

Fixes: 2f664823 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent cef8dac9

drivers/net/phy/at803x.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -425,8 +425,8 @@ static int at803x_parse_dt(struct phy_device *phydev)
		*/
		if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) \|\|
		at803x_match_phy_id(phydev, ATH8035_PHY_ID)) {
		priv->clk_25m_reg &= ~AT8035_CLK_OUT_MASK;
		priv->clk_25m_mask &= ~AT8035_CLK_OUT_MASK;
		priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
		priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
		}
		}

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