Commit b1d12868 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: adjust HDP write queue flushing for tlb invalidation 



Separate tlb invalidation and hdp flushing and move the HDP
flush to the caller.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 73c73240

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

+2 −0
Original line number Diff line number Diff line
@@ -247,6 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 
		}

	}

	mb();

	amdgpu_asic_flush_hdp(adev);

	amdgpu_gart_flush_gpu_tlb(adev, 0);

	return 0;

}
@@ -329,6 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 
		return r;



	mb();

	amdgpu_asic_flush_hdp(adev);

	amdgpu_gart_flush_gpu_tlb(adev, 0);

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+2 −0
Original line number Diff line number Diff line
@@ -856,6 +856,7 @@ restart: 
	if (vm->use_cpu_for_update) {

		/* Flush HDP */

		mb();

		amdgpu_asic_flush_hdp(adev);

		amdgpu_gart_flush_gpu_tlb(adev, 0);

	} else if (params.ib->length_dw == 0) {

		amdgpu_job_free(job);
@@ -1457,6 +1458,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, 
	if (vm->use_cpu_for_update) {

		/* Flush HDP */

		mb();

		amdgpu_asic_flush_hdp(adev);

		amdgpu_gart_flush_gpu_tlb(adev, 0);

	}

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+0 −2
Original line number Diff line number Diff line
@@ -360,8 +360,6 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 
static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,

					uint32_t vmid)

{

	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);



	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);

}

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+0 −3
Original line number Diff line number Diff line
@@ -432,9 +432,6 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 
static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,

					uint32_t vmid)

{

	/* flush hdp cache */

	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);



	/* bits 0-15 are the VM contexts0-15 */

	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);

}

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+0 −3
Original line number Diff line number Diff line
@@ -607,9 +607,6 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 
static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,

					uint32_t vmid)

{

	/* flush hdp cache */

	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);



	/* bits 0-15 are the VM contexts0-15 */

	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);

}

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