Commit b1c15668 authored Sep 11, 2018 by Dave Airlie

Merge tag 'drm-intel-next-2018-09-06-2' of...

Merge tag 'drm-intel-next-2018-09-06-2' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Merge tag 'gvt-next-2018-09-04'
drm-intel-next-2018-09-06-1:
UAPI Changes:
- GGTT coherency GETPARAM: GGTT has turned out to be non-coherent for some
  platforms, which we've failed to communicate to userspace so far. SNA was
  modified to do extra flushing on non-coherent GGTT access, while Mesa will
  mitigate by always requiring WC mapping (which is non-coherent anyway).
- Neuter Resource Streamer uAPI: There never really were users for the feature,
  so neuter it while keeping the interface bits for compatibility. This is a
  long due item from past.

Cross-subsystem Changes:
- Backmerge of branch drm-next-4.19 for DP_DPCD_REV_14 changes

Core Changes:
- None

Driver Changes:

- A load of Icelake (ICL) enabling patches (Paulo, Manasi)
- Enabled full PPGTT for IVB,VLV and HSW (Chris)
- Bugzilla #107113: Distribute DDB based on display resolutions (Mahesh)
- Bugzillas #100023,#107476,#94921: Support limited range DP displays (Jani)
- Bugzilla #107503: Increase LSPCON timeout (Fredrik)
- Avoid boosting GPU due to an occasional stall in interactive workloads (Chris)
- Apply GGTT coherency W/A only for affected systems instead of all (Chris)
- Fix for infinite link training loop for faulty USB-C MST hubs (Nathan)
- Keep KMS functional on Gen4 and earlier when GPU is wedged (Chris)
- Stop holding ppGTT reference from closed VMAs (Chris)
- Clear error registers after error capture (Lionel)
- Various Icelake fixes (Anusha, Jyoti, Ville, Tvrtko)
- Add missing Coffeelake (CFL) PCI IDs (Rodrigo)
- Flush execlists tasklet directly from reset-finish (Chris)
- Fix LPE audio runtime PM (Chris)
- Fix detection of out of range surface positions (GLK/CNL) (Ville)
- Remove wait-for-idle for PSR2 (Dhinakaran)
- Power down existing display hardware resources when display is disabled (Chris)
- Don't allow runtime power management if RC6 doesn't exist (Chris)
- Add debugging checks for runtime power management paths (Imre)
- Increase symmetry in display power init/fini paths (Imre)
- Isolate GVT specific macros from i915_reg.h (Lucas)
- Increase symmetry in power management enable/disable paths (Chris)
- Increase IP disable timeout to 100 ms to avoid DRM_ERROR (Imre)
- Fix memory leak from HDMI HDCP write function (Brian, Rodrigo)
- Reject Y/Yf tiling on interlaced modes (Ville)
- Use a cached mapping for the physical HWS on older gens (Chris)
- Force slow path of writing relocations to buffer if unable to write to userspace (Chris)
- Do a full device reset after being wedged (Chris)
- Keep forcewake counts over reset (in case of debugfs user) (Imre, Chris)
- Avoid false-positive errors from power wells during init (Imre)
- Reset engines forcibly in exchange of declaring whole device wedged (Mika)
- Reduce context HW ID lifetime in preparation for Icelake (Chris)
- Attempt to recover from module load failures (Chris)
- Keep select interrupts over a reset to avoid missing/losing them (Chris)
- GuC submission backend improvements (Jakub)
- Terminate context images with BB_END (Chris, Lionel)
- Make GCC evaluate GGTT view struct size assertions again (Ville)
- Add selftest to exercise suspend/hibernate code-paths for GEM (Chris)
- Use a full emulation of a user ppgtt context in selftests (Chris)
- Exercise resetting in the middle of a wait-on-fence in selftests (Chris)
- Fix coherency issues on selftests for Baytrail (Chris)
- Various other GEM fixes / self-test updates (Chris, Matt)
- GuC doorbell self-tests (Daniele)
- PSR mode control through debugfs for IGTs (Maarten)
- Degrade expected WM latency errors to DRM_DEBUG_KMS (Chris)
- Cope with errors better in MST link training (Dhinakaran)
- Fix WARN on KBL external displays (Azhar)
- Power well code cleanups (Imre)
- Fixes to PSR debugging (Dhinakaran)
- Make forcewake errors louder for easier catching in CI (WARNs) (Chris)
- Fortify tiling code against programmer errors (Chris)
- Bunch of fixes for CI exposed corner cases (multiple authors, mostly Chris)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180907105446.GA22860@jlahtine-desk.ger.corp.intel.com

parents 1f3eb346 a28957b8

drivers/gpu/drm/i915/Kconfig.debug

+12 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@ config DRM_I915_DEBUG
		select SW_SYNC # signaling validation framework (igt/syncobj*)
		select DRM_I915_SW_FENCE_DEBUG_OBJECTS
		select DRM_I915_SELFTEST
		select DRM_I915_DEBUG_RUNTIME_PM
		default n
		help
		Choose this option to turn on extra driver debugging that may affect
		@@ -167,3 +168,14 @@ config DRM_I915_DEBUG_VBLANK_EVADE
		the vblank.

		If in doubt, say "N".

		config DRM_I915_DEBUG_RUNTIME_PM
		bool "Enable extra state checking for runtime PM"
		depends on DRM_I915
		default n
		help
		Choose this option to turn on extra state checking for the
		runtime PM functionality. This may introduce overhead during
		driver loading, suspend and resume operations.

		If in doubt, say "N"

drivers/gpu/drm/i915/gvt/cfg_space.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,10 @@ static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {

		/**
		* vgpu_pci_cfg_mem_write - write virtual cfg space memory
		* @vgpu: target vgpu
		* @off: offset
		* @src: src ptr to write
		* @bytes: number of bytes
		*
		* Use this function to write virtual cfg space memory.
		* For standard cfg space, only RW bits can be changed,
		@@ -91,6 +95,10 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,

		/**
		* intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
		* @vgpu: target vgpu
		* @offset: offset
		* @p_data: return data ptr
		* @bytes: number of bytes to read
		*
		* Returns:
		* Zero on success, negative error code if failed.
		@@ -278,6 +286,10 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,

		/**
		* intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
		* @vgpu: target vgpu
		* @offset: offset
		* @p_data: write data ptr
		* @bytes: number of bytes to write
		*
		* Returns:
		* Zero on success, negative error code if failed.

drivers/gpu/drm/i915/gvt/cmd_parser.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -1840,6 +1840,8 @@ static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
		return ret;
		}

		static int mi_noop_index;

		static struct cmd_info cmd_info[] = {
		{"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},

		@@ -2525,7 +2527,12 @@ static int cmd_parser_exec(struct parser_exec_state *s)

		cmd = cmd_val(s, 0);

		/* fastpath for MI_NOOP */
		if (cmd == MI_NOOP)
		info = &cmd_info[mi_noop_index];
		else
		info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);

		if (info == NULL) {
		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
		cmd, get_opcode(cmd, s->ring_id),
		@@ -2928,6 +2935,8 @@ static int init_cmd_table(struct intel_gvt *gvt)
		kfree(e);
		return -EEXIST;
		}
		if (cmd_info[i].opcode == OP_MI_NOOP)
		mi_noop_index = i;

		INIT_HLIST_NODE(&e->hlist);
		add_cmd_entry(gvt, e);

drivers/gpu/drm/i915/gvt/display.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -462,6 +462,7 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
		/**
		* intel_vgpu_init_display- initialize vGPU virtual display emulation
		* @vgpu: a vGPU
		* @resolution: resolution index for intel_vgpu_edid
		*
		* This function is used to initialize vGPU virtual display emulation stuffs
		*

drivers/gpu/drm/i915/gvt/edid.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -340,6 +340,9 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
		/**
		* intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
		* @vgpu: a vGPU
		* @offset: reg offset
		* @p_data: data return buffer
		* @bytes: access data length
		*
		* This function is used to emulate gmbus register mmio read
		*
		@@ -365,6 +368,9 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
		/**
		* intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
		* @vgpu: a vGPU
		* @offset: reg offset
		* @p_data: data return buffer
		* @bytes: access data length
		*
		* This function is used to emulate gmbus register mmio write
		*
		@@ -437,6 +443,9 @@ static inline int get_aux_ch_reg(unsigned int offset)
		/**
		* intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
		* @vgpu: a vGPU
		* @port_idx: port index
		* @offset: reg offset
		* @p_data: write ptr
		*
		* This function is used to emulate AUX channel register write
		*

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