Commit b19b9282 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-4.18-rc4' of... 

Merge tag 'riscv-for-linus-4.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull RISC-V fixes from Palmer Dabbelt:
 "This contains a handful of fixes for the RISC-V port:

   - A fix to R_RISCV_ADD32/R_RISCV_SUB32 relocations that allows
     modules that use these to load correctly.

   - The removal of of_platform_populate(), which is obselete.

   - The removal of irq-riscv-intc.h, which is obselete.

   - A fix to PTRACE_SETREGSET.

   - Fixes that allow the RV32I kernel to build (at least for Zong, I've
     got another patch on the mailing list that's necessary on my setup :)).

  I've just given these a defconfig build test"

* tag 'riscv-for-linus-4.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  RISC-V: Fix PTRACE_SETREGSET bug.
  RISC-V: Don't include irq-riscv-intc.h
  riscv: remove unnecessary of_platform_populate call
  RISC-V: fix R_RISCV_ADD32/R_RISCV_SUB32 relocations
  RISC-V: Change variable type for 32-bit compatible
  RISC-V: Add definiion of extract symbol's index and type for 32-bit
  RISC-V: Select GENERIC_UCMPDI2 on RV32I
  RISC-V: Add conditional macro for zone of DMA32
parents 760885f2 9a6a5115

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ config ARCH_RV32I 
	select GENERIC_LIB_ASHLDI3

	select GENERIC_LIB_ASHRDI3

	select GENERIC_LIB_LSHRDI3

	select GENERIC_LIB_UCMPDI2



config ARCH_RV64I

	bool "RV64I"

arch/riscv/include/uapi/asm/elf.h

+7 −2
Original line number Diff line number Diff line
@@ -21,8 +21,13 @@ typedef struct user_regs_struct elf_gregset_t; 


typedef union __riscv_fp_state elf_fpregset_t;



#define ELF_RISCV_R_SYM(r_info) ((r_info) >> 32)

#define ELF_RISCV_R_TYPE(r_info) ((r_info) & 0xffffffff)

#if __riscv_xlen == 64

#define ELF_RISCV_R_SYM(r_info)		ELF64_R_SYM(r_info)

#define ELF_RISCV_R_TYPE(r_info)	ELF64_R_TYPE(r_info)

#else

#define ELF_RISCV_R_SYM(r_info)		ELF32_R_SYM(r_info)

#define ELF_RISCV_R_TYPE(r_info)	ELF32_R_TYPE(r_info)

#endif



/*

 * RISC-V relocation types

arch/riscv/kernel/irq.c

+0 −4
Original line number Diff line number Diff line
@@ -16,10 +16,6 @@ 
#include <linux/irqchip.h>

#include <linux/irqdomain.h>



#ifdef CONFIG_RISCV_INTC

#include <linux/irqchip/irq-riscv-intc.h>

#endif



void __init init_IRQ(void)

{

	irqchip_init();

arch/riscv/kernel/module.c

+13 −13
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static int apply_r_riscv_64_rela(struct module *me, u32 *location, Elf_Addr v) 
static int apply_r_riscv_branch_rela(struct module *me, u32 *location,

				     Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	u32 imm12 = (offset & 0x1000) << (31 - 12);

	u32 imm11 = (offset & 0x800) >> (11 - 7);

	u32 imm10_5 = (offset & 0x7e0) << (30 - 10);
@@ -50,7 +50,7 @@ static int apply_r_riscv_branch_rela(struct module *me, u32 *location, 
static int apply_r_riscv_jal_rela(struct module *me, u32 *location,

				  Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	u32 imm20 = (offset & 0x100000) << (31 - 20);

	u32 imm19_12 = (offset & 0xff000);

	u32 imm11 = (offset & 0x800) << (20 - 11);
@@ -63,7 +63,7 @@ static int apply_r_riscv_jal_rela(struct module *me, u32 *location, 
static int apply_r_riscv_rcv_branch_rela(struct module *me, u32 *location,

					 Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	u16 imm8 = (offset & 0x100) << (12 - 8);

	u16 imm7_6 = (offset & 0xc0) >> (6 - 5);

	u16 imm5 = (offset & 0x20) >> (5 - 2);
@@ -78,7 +78,7 @@ static int apply_r_riscv_rcv_branch_rela(struct module *me, u32 *location, 
static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location,

				       Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	u16 imm11 = (offset & 0x800) << (12 - 11);

	u16 imm10 = (offset & 0x400) >> (10 - 8);

	u16 imm9_8 = (offset & 0x300) << (12 - 11);
@@ -96,7 +96,7 @@ static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location, 
static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location,

					 Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	s32 hi20;



	if (offset != (s32)offset) {
@@ -178,7 +178,7 @@ static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location, 
static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location,

				       Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	s32 hi20;



	/* Always emit the got entry */
@@ -200,7 +200,7 @@ static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location, 
static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location,

				       Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	s32 fill_v = offset;

	u32 hi20, lo12;
@@ -227,7 +227,7 @@ static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, 
static int apply_r_riscv_call_rela(struct module *me, u32 *location,

				   Elf_Addr v)

{

	s64 offset = (void *)v - (void *)location;

	ptrdiff_t offset = (void *)v - (void *)location;

	s32 fill_v = offset;

	u32 hi20, lo12;
@@ -263,14 +263,14 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, 
static int apply_r_riscv_add32_rela(struct module *me, u32 *location,

				    Elf_Addr v)

{

	*(u32 *)location += (*(u32 *)v);

	*(u32 *)location += (u32)v;

	return 0;

}



static int apply_r_riscv_sub32_rela(struct module *me, u32 *location,

				    Elf_Addr v)

{

	*(u32 *)location -= (*(u32 *)v);

	*(u32 *)location -= (u32)v;

	return 0;

}
@@ -347,7 +347,7 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, 
			unsigned int j;



			for (j = 0; j < sechdrs[relsec].sh_size / sizeof(*rel); j++) {

				u64 hi20_loc =

				unsigned long hi20_loc =

					sechdrs[sechdrs[relsec].sh_info].sh_addr

					+ rel[j].r_offset;

				u32 hi20_type = ELF_RISCV_R_TYPE(rel[j].r_info);
@@ -360,12 +360,12 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, 
					Elf_Sym *hi20_sym =

						(Elf_Sym *)sechdrs[symindex].sh_addr

						+ ELF_RISCV_R_SYM(rel[j].r_info);

					u64 hi20_sym_val =

					unsigned long hi20_sym_val =

						hi20_sym->st_value

						+ rel[j].r_addend;



					/* Calculate lo12 */

					u64 offset = hi20_sym_val - hi20_loc;

					size_t offset = hi20_sym_val - hi20_loc;

					if (IS_ENABLED(CONFIG_MODULE_SECTIONS)

					    && hi20_type == R_RISCV_GOT_HI20) {

						offset = module_emit_got_entry(

arch/riscv/kernel/ptrace.c

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ static int riscv_gpr_set(struct task_struct *target, 
	struct pt_regs *regs;



	regs = task_pt_regs(target);

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &regs, 0, -1);

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs, 0, -1);

	return ret;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE