Commit b177571b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.15-tag2' of... 

Merge tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the second display unit clock on RZ/G1E,
  - Add git repository to MAINTAINERS,
  - Add suspend/resume support for R-Car Gen3 CPG/MSSR,
  - Small fixes and cleanups.

* tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Restore R clock during resume
  clk: renesas: rcar-gen3: Restore SDHI clocks during resume
  clk: renesas: div6: Restore clock state during resume
  clk: renesas: cpg-mssr: Add support to restore core clocks during resume
  clk: renesas: cpg-mssr: Restore module clocks during resume
  MAINTAINERS: Add git repository to Renesas clock driver section
  clk: renesas: cpg-mssr: Add du1 clock to R8A7745
  clk: renesas: rz: clk-rz is meant for RZ/A1
  clk: renesas: r8a77995: Correct parent clock of INTC-AP
  clk: renesas: r8a7796: Correct parent clock of INTC-AP
  clk: renesas: r8a7795: Correct parent clock of INTC-AP
parents 319663c7 3f7a4d08

Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt

+2 −2
Original line number Diff line number Diff line 
* Renesas RZ Clock Pulse Generator (CPG)

* Renesas RZ/A1 Clock Pulse Generator (CPG)



The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable

The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable

CPU and GPU clocks, and several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -11428,6 +11428,7 @@ F: include/linux/rpmsg/ 
RENESAS CLOCK DRIVERS

M:	Geert Uytterhoeven <geert+renesas@glider.be>

L:	linux-renesas-soc@vger.kernel.org

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas

S:	Supported

F:	drivers/clk/renesas/

drivers/clk/renesas/clk-div6.c

+36 −2
Original line number Diff line number Diff line
@@ -14,8 +14,10 @@ 
#include <linux/init.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/notifier.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/pm.h>

#include <linux/slab.h>



#include "clk-div6.h"
@@ -32,6 +34,7 @@ 
 * @src_shift: Shift to access the register bits to select the parent clock

 * @src_width: Number of register bits to select the parent clock (may be 0)

 * @parents: Array to map from valid parent clocks indices to hardware indices

 * @nb: Notifier block to save/restore clock state for system resume

 */

struct div6_clock {

	struct clk_hw hw;
@@ -40,6 +43,7 @@ struct div6_clock { 
	u32 src_shift;

	u32 src_width;

	u8 *parents;

	struct notifier_block nb;

};



#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
@@ -176,6 +180,29 @@ static const struct clk_ops cpg_div6_clock_ops = { 
	.set_rate = cpg_div6_clock_set_rate,

};



static int cpg_div6_clock_notifier_call(struct notifier_block *nb,

					unsigned long action, void *data)

{

	struct div6_clock *clock = container_of(nb, struct div6_clock, nb);



	switch (action) {

	case PM_EVENT_RESUME:

		/*

		 * TODO: This does not yet support DIV6 clocks with multiple

		 * parents, as the parent selection bits are not restored.

		 * Fortunately so far such DIV6 clocks are found only on

		 * R/SH-Mobile SoCs, while the resume functionality is only

		 * needed on R-Car Gen3.

		 */

		if (__clk_get_enable_count(clock->hw.clk))

			cpg_div6_clock_enable(&clock->hw);

		else

			cpg_div6_clock_disable(&clock->hw);

		return NOTIFY_OK;

	}



	return NOTIFY_DONE;

}



/**

 * cpg_div6_register - Register a DIV6 clock
@@ -183,11 +210,13 @@ static const struct clk_ops cpg_div6_clock_ops = { 
 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)

 * @parent_names: Array containing the names of the parent clocks

 * @reg: Mapped register used to control the DIV6 clock

 * @notifiers: Optional notifier chain to save/restore state for system resume

 */

struct clk * __init cpg_div6_register(const char *name,

				      unsigned int num_parents,

				      const char **parent_names,

				      void __iomem *reg)

				      void __iomem *reg,

				      struct raw_notifier_head *notifiers)

{

	unsigned int valid_parents;

	struct clk_init_data init;
@@ -258,6 +287,11 @@ struct clk * __init cpg_div6_register(const char *name, 
	if (IS_ERR(clk))

		goto free_parents;



	if (notifiers) {

		clock->nb.notifier_call = cpg_div6_clock_notifier_call;

		raw_notifier_chain_register(notifiers, &clock->nb);

	}



	return clk;



free_parents:
@@ -301,7 +335,7 @@ static void __init cpg_div6_clock_init(struct device_node *np) 
	for (i = 0; i < num_parents; i++)

		parent_names[i] = of_clk_get_parent_name(np, i);



	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg);

	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);

	if (IS_ERR(clk)) {

		pr_err("%s: failed to register %s DIV6 clock (%ld)\n",

		       __func__, np->name, PTR_ERR(clk));

drivers/clk/renesas/clk-div6.h

+2 −1
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#define __RENESAS_CLK_DIV6_H__



struct clk *cpg_div6_register(const char *name, unsigned int num_parents,

			      const char **parent_names, void __iomem *reg);

			      const char **parent_names, void __iomem *reg,

			      struct raw_notifier_head *notifiers);



#endif

drivers/clk/renesas/clk-rz.c

+1 −1
Original line number Diff line number Diff line 
/*

 * rz Core CPG Clocks

 * RZ/A1 Core CPG Clocks

 *

 * Copyright (C) 2013 Ideas On Board SPRL

 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>

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