Commit b1713739 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "A fairly quiet release for SPI, nothing really going on in the core
  although there's been quite a bit of driver related activity.

  This includes the addition of some shared code in drivers/memory for
  the Renesas RPC-IF which is used by a newly added SPI driver, the
  memory subsystem doesn't seem to have a fixed maintainer at the minute
  and this seemed like the most sensible way to get that hardware
  supported.

   - Quite a few cleanups and optimizations for the Altera, Qualcomm
     GENI, sun6i and lantiq drivers.

   - Several more GPIO descriptor conversions.

   - Move the Cadence QuadSPI driver from drivers/mtd to drivers/spi.

   - New support for Mediatek MT8192 and Renesas RPC-IF, R8A7742 and
     R8A774e1"

* tag 'spi-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (119 commits)
  dt-bindings: lpspi: New property in document DT bindings for LPSPI
  spi: lpspi: fix using CS discontinuously on i.MX8DXLEVK
  spi: lpspi: remove unused fsl_lpspi->chipselect
  spi: lpspi: Fix kernel warning dump when probe fail after calling spi_register
  spi: rockchip: Fix error in SPI slave pio read
  spi: rockchip: Support 64-location deep FIFOs
  spi: rockchip: Config spi rx dma burst size depend on xfer length
  spi: spi-topcliff-pch: drop call to wakeup-disable
  spi: spidev: Align buffers for DMA
  spi: correct kernel-doc inconsistency
  spi: sun4i: update max transfer size reported
  spi: imx: enable runtime pm support
  spi: update bindings for MT8192 SoC
  spi: mediatek: add spi support for mt8192 IC
  spi: Add bindings for Lightning Mountain SoC
  spi: lantiq: Add support to Lightning Mountain SoC
  spi: lantiq: Move interrupt configuration to SoC specific data structure
  spi: lantiq: Add fifo size bit mask in SoC specific data structure
  spi: lantiq: Add support to acknowledge interrupt
  spi: lantiq: Move interrupt control register offesets to SoC specific data structure
  ...
parents bbb83990 11ba2822

Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas Reduced Pin Count Interface (RPC-IF)



maintainers:

  - Sergei Shtylyov <sergei.shtylyov@gmail.com>



description: |

  Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to

  be accessed via the external address space read mode or the manual mode.



  The flash chip itself should be represented by a subnode of the RPC-IF node.

  The flash interface is selected based on the "compatible" property of this

  subnode:

  - if it contains "jedec,spi-nor", then SPI is used;

  - if it contains "cfi-flash", then HyperFlash is used.



allOf:

  - $ref: "/schemas/spi/spi-controller.yaml#"



properties:

  compatible:

    items:

      - enum:

        - renesas,r8a77970-rpc-if       # R-Car V3M

        - renesas,r8a77980-rpc-if       # R-Car V3H

        - renesas,r8a77995-rpc-if       # R-Car D3

      - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 device



  reg:

    items:

      - description: RPC-IF registers

      - description: direct mapping read mode area

      - description: write buffer area



  reg-names:

    items:

      - const: regs

      - const: dirmap

      - const: wbuf



  clocks:

    maxItems: 1



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



patternProperties:

  "flash@[0-9a-f]+$":

    type: object

    properties:

      compatible:

        enum:

          - cfi-flash

          - jedec,spi-nor



examples:

  - |

    #include <dt-bindings/clock/renesas-cpg-mssr.h>

    #include <dt-bindings/power/r8a77995-sysc.h>



    spi@ee200000 {

      compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";

      reg = <0xee200000 0x200>,

            <0x08000000 0x4000000>,

            <0xee208000 0x100>;

      reg-names = "regs", "dirmap", "wbuf";

      clocks = <&cpg CPG_MOD 917>;

      power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;

      resets = <&cpg 917>;

      #address-cells = <1>;

      #size-cells = <0>;



      flash@0 {

        compatible = "jedec,spi-nor";

        reg = <0>;

        spi-max-frequency = <40000000>;

        spi-tx-bus-width = <1>;

        spi-rx-bus-width = <1>;

      };

    };

Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt

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* Freescale (Enhanced) Configurable Serial Peripheral Interface

  (CSPI/eCSPI) for i.MX



Required properties:

- compatible :

  - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1

  - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21

  - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27

  - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31

  - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35

  - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51

  - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc

  - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8MQ

  - "fsl,imx8mm-ecspi" for SPI compatible with the one integrated on i.MX8MM

  - "fsl,imx8mn-ecspi" for SPI compatible with the one integrated on i.MX8MN

  - "fsl,imx8mp-ecspi" for SPI compatible with the one integrated on i.MX8MP

- reg : Offset and length of the register set for the device

- interrupts : Should contain CSPI/eCSPI interrupt

- clocks : Clock specifiers for both ipg and per clocks.

- clock-names : Clock names should include both "ipg" and "per"

See the clock consumer binding,

	Documentation/devicetree/bindings/clock/clock-bindings.txt



Recommended properties:

- cs-gpios : GPIOs to use as chip selects, see spi-bus.txt.  While the native chip

select lines can be used, they appear to always generate a pulse between each

word of a transfer.  Most use cases will require GPIO based chip selects to

generate a valid transaction.



Optional properties:

- num-cs :  Number of total chip selects, see spi-bus.txt.

- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,

Documentation/devicetree/bindings/dma/dma.txt.

- dma-names: DMA request names, if present, should include "tx" and "rx".

- fsl,spi-rdy-drctl: Integer, representing the value of DRCTL, the register

controlling the SPI_READY handling. Note that to enable the DRCTL consideration,

the SPI_READY mode-flag needs to be set too.

Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).



Obsolete properties:

- fsl,spi-num-chipselects : Contains the number of the chipselect



Example:



ecspi@70010000 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "fsl,imx51-ecspi";

	reg = <0x70010000 0x4000>;

	interrupts = <36>;

	cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */

		   <&gpio3 25 0>; /* GPIO3_25 */

	dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;

	dma-names = "rx", "tx";

	fsl,spi-rdy-drctl = <1>;

};

Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX



maintainers:

  - Shawn Guo <shawn.guo@linaro.org>



allOf:

  - $ref: "/schemas/spi/spi-controller.yaml#"



properties:

  compatible:

    oneOf:

      - const: fsl,imx1-cspi

      - const: fsl,imx21-cspi

      - const: fsl,imx27-cspi

      - const: fsl,imx31-cspi

      - const: fsl,imx35-cspi

      - const: fsl,imx51-ecspi

      - const: fsl,imx53-ecspi

      - items:

        - enum:

          - fsl,imx50-ecspi

          - fsl,imx6q-ecspi

          - fsl,imx6sx-ecspi

          - fsl,imx6sl-ecspi

          - fsl,imx6sll-ecspi

          - fsl,imx6ul-ecspi

          - fsl,imx7d-ecspi

          - fsl,imx8mq-ecspi

          - fsl,imx8mm-ecspi

          - fsl,imx8mn-ecspi

          - fsl,imx8mp-ecspi

        - const: fsl,imx51-ecspi



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: SoC SPI ipg clock

      - description: SoC SPI per clock



  clock-names:

    items:

      - const: ipg

      - const: per



  dmas:

    items:

      - description: DMA controller phandle and request line for RX

      - description: DMA controller phandle and request line for TX



  dma-names:

    items:

      - const: rx

      - const: tx



  fsl,spi-rdy-drctl:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Integer, representing the value of DRCTL, the register controlling

      the SPI_READY handling. Note that to enable the DRCTL consideration,

      the SPI_READY mode-flag needs to be set too.

      Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).

    enum: [0, 1, 2]



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx5-clock.h>



    spi@70010000 {

        #address-cells = <1>;

        #size-cells = <0>;

        compatible = "fsl,imx51-ecspi";

        reg = <0x70010000 0x4000>;

        interrupts = <36>;

        clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,

                 <&clks IMX5_CLK_ECSPI1_PER_GATE>;

        clock-names = "ipg", "per";

    };

Documentation/devicetree/bindings/spi/mxs-spi.txt

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* Freescale MX233/MX28 SSP/SPI



Required properties:

- compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28"

- reg: Offset and length of the register set for the device

- interrupts: Should contain SSP ERROR interrupt

- dmas: DMA specifier, consisting of a phandle to DMA controller node

  and SSP DMA channel ID.

  Refer to dma.txt and fsl-mxs-dma.txt for details.

- dma-names: Must be "rx-tx".



Optional properties:

- clock-frequency : Input clock frequency to the SPI block in Hz.

		    Default is 160000000 Hz.



Example:



ssp0: ssp@80010000 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "fsl,imx28-spi";

	reg = <0x80010000 0x2000>;

	interrupts = <96>;

	dmas = <&dma_apbh 0>;

	dma-names = "rx-tx";

};

Documentation/devicetree/bindings/spi/mxs-spi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/mxs-spi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale MX233/MX28 SSP/SPI



maintainers:

  - Marek Vasut <marex@denx.de>



allOf:

  - $ref: "/schemas/spi/spi-controller.yaml#"



properties:

  compatible:

    enum:

      - fsl,imx23-spi

      - fsl,imx28-spi



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  dmas:

    maxItems: 1



  dma-names:

    const: rx-tx



  clock-frequency:

    description: input clock frequency to the SPI block in Hz.

    default: 160000000



required:

  - compatible

  - reg

  - interrupts

  - dmas

  - dma-names



unevaluatedProperties: false



examples:

  - |

    spi@80010000 {

        #address-cells = <1>;

        #size-cells = <0>;

        compatible = "fsl,imx28-spi";

        reg = <0x80010000 0x2000>;

        interrupts = <96>;

        dmas = <&dma_apbh 0>;

        dma-names = "rx-tx";

    };

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