clk: sunxi-ng: r40: Add max. rate constraint to video PLLs (b16fb669) · Commits · 戴 / test

Video PLLs on R40 can be set to higher rate that it is actually supported by HW. Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP clock driver. Interestengly, user manual specifies maximum frequency to be 600 MHz. Historically, this data was wrong in some user manuals for other SoCs, so more faith is put in BSP clock driver. Signed-off-by:

Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by:

Maxime Ripard <maxime.ripard@bootlin.com>

drivers/clk/sunxi-ng/ccu-sun8i-r40.c

+26 −26

Original line number	Diff line number	Diff line
		@@ -65,10 +65,10 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
		BIT(28), /* lock */
		CLK_SET_RATE_UNGATE);

		/* TODO: The result of N/M is required to be in [8, 25] range. */
		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
		"osc24M", 0x0010,
		192000000, /* Minimum rate */
		1008000000, /* Maximum rate */
		8, 7, /* N */
		0, 4, /* M */
		BIT(24), /* frac enable */
		@@ -152,10 +152,10 @@ static struct ccu_nk pll_periph1_clk = {
		},
		};

		/* TODO: The result of N/M is required to be in [8, 25] range. */
		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
		"osc24M", 0x030,
		192000000, /* Minimum rate */
		1008000000, /* Maximum rate */
		8, 7, /* N */
		0, 4, /* M */
		BIT(24), /* frac enable */

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