Commit b16b2a2f authored by Paulo Zanoni's avatar Paulo Zanoni
Browse files

drm/i915: fully convert the IRQ initialization macros to intel_uncore 



Make them take the uncore argument from the caller instead of passing
the implicit &dev_priv->uncore directly. This will allow us to finally
pass something that's not dev_priv->uncore in the future, and gets rid
of the implicit variables in register macros.

v2: Rebase on top of the newer patches.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190410235344.31199-6-paulo.r.zanoni@intel.com
parent 65f42cdc

drivers/gpu/drm/i915/i915_irq.c

+88 −56
Original line number Diff line number Diff line
@@ -165,18 +165,18 @@ static void gen2_irq_reset(struct intel_uncore *uncore) 
	intel_uncore_posting_read16(uncore, GEN2_IIR);

}



#define GEN8_IRQ_RESET_NDX(type, which) \

#define GEN8_IRQ_RESET_NDX(uncore, type, which) \

({ \

	unsigned int which_ = which; \

	gen3_irq_reset(&dev_priv->uncore, GEN8_##type##_IMR(which_), \

	gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \

		       GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \

})



#define GEN3_IRQ_RESET(type) \

	gen3_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER)

#define GEN3_IRQ_RESET(uncore, type) \

	gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)



#define GEN2_IRQ_RESET() \

	gen2_irq_reset(&dev_priv->uncore)

#define GEN2_IRQ_RESET(uncore) \

	gen2_irq_reset(uncore)



/*

 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
@@ -233,23 +233,23 @@ static void gen2_irq_init(struct intel_uncore *uncore, 
	intel_uncore_posting_read16(uncore, GEN2_IMR);

}



#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \

#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \

({ \

	unsigned int which_ = which; \

	gen3_irq_init(&dev_priv->uncore, \

	gen3_irq_init((uncore), \

		      GEN8_##type##_IMR(which_), imr_val, \

		      GEN8_##type##_IER(which_), ier_val, \

		      GEN8_##type##_IIR(which_)); \

})



#define GEN3_IRQ_INIT(type, imr_val, ier_val) \

	gen3_irq_init(&dev_priv->uncore, \

#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \

	gen3_irq_init((uncore), \

		      type##IMR, imr_val, \

		      type##IER, ier_val, \

		      type##IIR)



#define GEN2_IRQ_INIT(imr_val, ier_val) \

	gen2_irq_init(&dev_priv->uncore, imr_val, ier_val)

#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \

	gen2_irq_init((uncore), imr_val, ier_val)



static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
@@ -3365,10 +3365,12 @@ static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv) 


static void ibx_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	if (HAS_PCH_NOP(dev_priv))

		return;



	GEN3_IRQ_RESET(SDE);

	GEN3_IRQ_RESET(uncore, SDE);



	if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))

		I915_WRITE(SERR_INT, 0xffffffff);
@@ -3396,13 +3398,17 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev) 


static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)

{

	GEN3_IRQ_RESET(GT);

	struct intel_uncore *uncore = &dev_priv->uncore;



	GEN3_IRQ_RESET(uncore, GT);

	if (INTEL_GEN(dev_priv) >= 6)

		GEN3_IRQ_RESET(GEN6_PM);

		GEN3_IRQ_RESET(uncore, GEN6_PM);

}



static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	if (IS_CHERRYVIEW(dev_priv))

		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

	else
@@ -3413,12 +3419,14 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 


	i9xx_pipestat_irq_reset(dev_priv);



	GEN3_IRQ_RESET(VLV_);

	GEN3_IRQ_RESET(uncore, VLV_);

	dev_priv->irq_mask = ~0u;

}



static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	u32 pipestat_mask;

	u32 enable_mask;

	enum pipe pipe;
@@ -3443,7 +3451,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 


	dev_priv->irq_mask = ~enable_mask;



	GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);

	GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);

}



/* drm_dma.h hooks
@@ -3451,8 +3459,9 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 
static void ironlake_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;



	GEN3_IRQ_RESET(DE);

	GEN3_IRQ_RESET(uncore, DE);

	if (IS_GEN(dev_priv, 7))

		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -3483,15 +3492,18 @@ static void valleyview_irq_reset(struct drm_device *dev) 


static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)

{

	GEN8_IRQ_RESET_NDX(GT, 0);

	GEN8_IRQ_RESET_NDX(GT, 1);

	GEN8_IRQ_RESET_NDX(GT, 2);

	GEN8_IRQ_RESET_NDX(GT, 3);

	struct intel_uncore *uncore = &dev_priv->uncore;



	GEN8_IRQ_RESET_NDX(uncore, GT, 0);

	GEN8_IRQ_RESET_NDX(uncore, GT, 1);

	GEN8_IRQ_RESET_NDX(uncore, GT, 2);

	GEN8_IRQ_RESET_NDX(uncore, GT, 3);

}



static void gen8_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;

	int pipe;



	gen8_master_intr_disable(dev_priv->uncore.regs);
@@ -3504,11 +3516,11 @@ static void gen8_irq_reset(struct drm_device *dev) 
	for_each_pipe(dev_priv, pipe)

		if (intel_display_power_is_enabled(dev_priv,

						   POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);

			GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);



	GEN3_IRQ_RESET(GEN8_DE_PORT_);

	GEN3_IRQ_RESET(GEN8_DE_MISC_);

	GEN3_IRQ_RESET(GEN8_PCU_);

	GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);

	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);

	GEN3_IRQ_RESET(uncore, GEN8_PCU_);



	if (HAS_PCH_SPLIT(dev_priv))

		ibx_irq_reset(dev_priv);
@@ -3534,6 +3546,7 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) 
static void gen11_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_uncore *uncore = &dev_priv->uncore;

	int pipe;



	gen11_master_intr_disable(dev_priv->uncore.regs);
@@ -3548,21 +3561,23 @@ static void gen11_irq_reset(struct drm_device *dev) 
	for_each_pipe(dev_priv, pipe)

		if (intel_display_power_is_enabled(dev_priv,

						   POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);

			GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);



	GEN3_IRQ_RESET(GEN8_DE_PORT_);

	GEN3_IRQ_RESET(GEN8_DE_MISC_);

	GEN3_IRQ_RESET(GEN11_DE_HPD_);

	GEN3_IRQ_RESET(GEN11_GU_MISC_);

	GEN3_IRQ_RESET(GEN8_PCU_);

	GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);

	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);

	GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);

	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);

	GEN3_IRQ_RESET(uncore, GEN8_PCU_);



	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)

		GEN3_IRQ_RESET(SDE);

		GEN3_IRQ_RESET(uncore, SDE);

}



void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,

				     u8 pipe_mask)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;

	enum pipe pipe;
@@ -3574,7 +3589,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 
	}



	for_each_pipe_masked(dev_priv, pipe, pipe_mask)

		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,

		GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,

				  dev_priv->de_irq_mask[pipe],

				  ~dev_priv->de_irq_mask[pipe] | extra_ier);
@@ -3584,6 +3599,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,

				     u8 pipe_mask)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	enum pipe pipe;



	spin_lock_irq(&dev_priv->irq_lock);
@@ -3594,7 +3610,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 
	}



	for_each_pipe_masked(dev_priv, pipe, pipe_mask)

		GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);

		GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);



	spin_unlock_irq(&dev_priv->irq_lock);
@@ -3605,13 +3621,14 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 
static void cherryview_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;



	I915_WRITE(GEN8_MASTER_IRQ, 0);

	POSTING_READ(GEN8_MASTER_IRQ);



	gen8_gt_irq_reset(dev_priv);



	GEN3_IRQ_RESET(GEN8_PCU_);

	GEN3_IRQ_RESET(uncore, GEN8_PCU_);



	spin_lock_irq(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
@@ -3896,6 +3913,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) 
static void gen5_gt_irq_postinstall(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 pm_irqs, gt_irqs;



	pm_irqs = gt_irqs = 0;
@@ -3914,7 +3932,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) 
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;

	}



	GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);

	GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs);



	if (INTEL_GEN(dev_priv) >= 6) {

		/*
@@ -3927,13 +3945,14 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) 
		}



		dev_priv->pm_imr = 0xffffffff;

		GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);

		GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs);

	}

}



static int ironlake_irq_postinstall(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 display_mask, extra_mask;



	if (INTEL_GEN(dev_priv) >= 7) {
@@ -3952,7 +3971,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) 
	}



	if (IS_HASWELL(dev_priv)) {

		gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);

		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);

		intel_psr_irq_control(dev_priv, dev_priv->psr.debug);

		display_mask |= DE_EDP_PSR_INT_HSW;

	}
@@ -3961,7 +3980,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) 


	ibx_irq_pre_postinstall(dev);



	GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);

	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,

		      display_mask | extra_mask);



	gen5_gt_irq_postinstall(dev);
@@ -4031,6 +4051,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev) 


static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	/* These are interrupts we'll toggle with the ring mask register */

	u32 gt_interrupts[] = {

		(GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
@@ -4051,18 +4073,20 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) 


	dev_priv->pm_ier = 0x0;

	dev_priv->pm_imr = ~dev_priv->pm_ier;

	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);

	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);

	GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);

	GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);

	/*

	 * RPS interrupts will get enabled/disabled on demand when RPS itself

	 * is enabled/disabled. Same wil be the case for GuC interrupts.

	 */

	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);

	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);

	GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);

	GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);

}



static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;

	u32 de_pipe_enables;

	u32 de_port_masked = GEN8_AUX_CHANNEL_A;
@@ -4098,7 +4122,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 
	else if (IS_BROADWELL(dev_priv))

		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;



	gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);

	gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);

	intel_psr_irq_control(dev_priv, dev_priv->psr.debug);



	for_each_pipe(dev_priv, pipe) {
@@ -4106,20 +4130,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 


		if (intel_display_power_is_enabled(dev_priv,

				POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,

			GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,

					  dev_priv->de_irq_mask[pipe],

					  de_pipe_enables);

	}



	GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);

	GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);

	GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);

	GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);



	if (INTEL_GEN(dev_priv) >= 11) {

		u32 de_hpd_masked = 0;

		u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |

				     GEN11_DE_TBT_HOTPLUG_MASK;



		GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);

		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,

			      de_hpd_enables);

		gen11_hpd_detection_setup(dev_priv);

	} else if (IS_GEN9_LP(dev_priv)) {

		bxt_hpd_detection_setup(dev_priv);
@@ -4191,6 +4216,7 @@ static void icp_irq_postinstall(struct drm_device *dev) 
static int gen11_irq_postinstall(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 gu_misc_masked = GEN11_GU_MISC_GSE;



	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
@@ -4199,7 +4225,7 @@ static int gen11_irq_postinstall(struct drm_device *dev) 
	gen11_gt_irq_postinstall(dev_priv);

	gen8_de_irq_postinstall(dev_priv);



	GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);

	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);



	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
@@ -4229,15 +4255,17 @@ static int cherryview_irq_postinstall(struct drm_device *dev) 
static void i8xx_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;



	i9xx_pipestat_irq_reset(dev_priv);



	GEN2_IRQ_RESET();

	GEN2_IRQ_RESET(uncore);

}



static int i8xx_irq_postinstall(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;

	u16 enable_mask;



	I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4255,7 +4283,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev) 
		I915_MASTER_ERROR_INTERRUPT |

		I915_USER_INTERRUPT;



	GEN2_IRQ_INIT(dev_priv->irq_mask, enable_mask);

	GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);



	/* Interrupt setup is already guaranteed to be single-threaded, this is

	 * just to make the assert_spin_locked check happy. */
@@ -4391,6 +4419,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) 
static void i915_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;



	if (I915_HAS_HOTPLUG(dev_priv)) {

		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
@@ -4399,12 +4428,13 @@ static void i915_irq_reset(struct drm_device *dev) 


	i9xx_pipestat_irq_reset(dev_priv);



	GEN3_IRQ_RESET(GEN2_);

	GEN3_IRQ_RESET(uncore, GEN2_);

}



static int i915_irq_postinstall(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 enable_mask;



	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4431,7 +4461,7 @@ static int i915_irq_postinstall(struct drm_device *dev) 
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;

	}



	GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);

	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);



	/* Interrupt setup is already guaranteed to be single-threaded, this is

	 * just to make the assert_spin_locked check happy. */
@@ -4502,18 +4532,20 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) 
static void i965_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;



	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);

	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));



	i9xx_pipestat_irq_reset(dev_priv);



	GEN3_IRQ_RESET(GEN2_);

	GEN3_IRQ_RESET(uncore, GEN2_);

}



static int i965_irq_postinstall(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 enable_mask;

	u32 error_mask;
@@ -4551,7 +4583,7 @@ static int i965_irq_postinstall(struct drm_device *dev) 
	if (IS_G4X(dev_priv))

		enable_mask |= I915_BSD_USER_INTERRUPT;



	GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);

	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);



	/* Interrupt setup is already guaranteed to be single-threaded, this is

	 * just to make the assert_spin_locked check happy. */

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