ARM: dts: r7s72100: add soc node (b1548238) · Commits · 戴 / test

Add soc node to represent the bus and move all nodes with a base address into this node. This is consistent with handling of R-Car Gen3 and Gen2 SoCs in mainline. It is intended to migrate other Renesas ARM-based SoCs to this scheme. The ordering is derived from simply moving each node with an address up to before any nodes without a base address that occur before the soc node. To improve maintainability follow-up patches will sort subnodes of both the new soc node and the root node. This patch should not introduce any functional change. Signed-off-by:

Simon Horman <horms+renesas@verge.net.au> Reviewed-by:

Geert Uytterhoeven <geert+renesas@glider.be>

arch/arm/boot/dts/r7s72100.dtsi

+459 −451

Original line number	Diff line number	Diff line
		@@ -15,7 +15,6 @@

		/ {
		compatible = "renesas,r7s72100";
		interrupt-parent = <&gic>;
		#address-cells = <1>;
		#size-cells = <1>;

		@@ -87,6 +86,29 @@
		clock-mult = <1>;
		clock-div = <12>;
		};
		};

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a9";
		reg = <0>;
		clock-frequency = <400000000>;
		clocks = <&cpg_clocks R7S72100_CLK_I>;
		next-level-cache = <&L2>;
		};
		};

		soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@fcfe0000 {
		@@ -192,21 +214,6 @@
		>;
		clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
		};
		};

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a9";
		reg = <0>;
		clock-frequency = <400000000>;
		clocks = <&cpg_clocks R7S72100_CLK_I>;
		next-level-cache = <&L2>;
		};
		};

		pinctrl: pin-controller@fcfe3000 {
		compatible = "renesas,r7s72100-ports";
		@@ -688,3 +695,4 @@
		status = "disabled";
		};
		};
		};

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