Commit b1286f4e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm 

Pull ARM updates from Russell King:
 "Here's the updates for ARM for this merge window, which cover quite a
  variety of areas.

  There's a bunch of patch series from Will tackling various bugs like
  the PROT_NONE handling, ASID allocation, cluster boot protocol and
  ASID TLB tagging updates.

  We move to a build-time sorted exception table rather than doing the
  sorting at run-time, add support for the secure computing filter, and
  some updates to the perf code.  We also have sorted out the placement
  of some headers, fixed some build warnings, fixed some hotplug
  problems with the per-cpu TWD code."

* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (73 commits)
  ARM: 7594/1: Add .smp entry for REALVIEW_EB
  ARM: 7599/1: head: Remove boot-time HYP mode check for v5 and below
  ARM: 7598/1: net: bpf_jit_32: fix sp-relative load/stores offsets.
  ARM: 7595/1: syscall: rework ordering in syscall_trace_exit
  ARM: 7596/1: mmci: replace readsl/writesl with ioread32_rep/iowrite32_rep
  ARM: 7597/1: net: bpf_jit_32: fix kzalloc gfp/size mismatch.
  ARM: 7593/1: nommu: do not enable DCACHE_WORD_ACCESS when !CONFIG_MMU
  ARM: 7592/1: nommu: prevent generation of kernel unaligned memory accesses
  ARM: 7591/1: nommu: Enable the strict alignment (CR_A) bit only if ARCH < v6
  ARM: 7590/1: /proc/interrupts: limit the display of IPIs to online CPUs only
  ARM: 7587/1: implement optimized percpu variable access
  ARM: 7589/1: integrator: pass the lm resource to amba
  ARM: 7588/1: amba: create a resource parent registrator
  ARM: 7582/2: rename kvm_seq to vmalloc_seq so to avoid confusion with KVM
  ARM: 7585/1: kernel: fix nr_cpu_ids check in DT logical map init
  ARM: 7584/1: perf: fix link error when CONFIG_HW_PERF_EVENTS is not selected
  ARM: gic: use a private mapping for CPU target interfaces
  ARM: kernel: add logical mappings look-up
  ARM: kernel: add cpu logical map DT init in setup_arch
  ARM: kernel: add device tree init map function
  ...
parents 6facac1a 0fa5d399

Documentation/devicetree/bindings/arm/cpus.txt

0 → 100644
+77 −0
Original line number Diff line number Diff line 
* ARM CPUs binding description



The device tree allows to describe the layout of CPUs in a system through

the "cpus" node, which in turn contains a number of subnodes (ie "cpu")

defining properties for every cpu.



Bindings for CPU nodes follow the ePAPR standard, available from:



http://devicetree.org



For the ARM architecture every CPU node must contain the following properties:



- device_type:	must be "cpu"

- reg:		property matching the CPU MPIDR[23:0] register bits

		reg[31:24] bits must be set to 0

- compatible:	should be one of:

		"arm,arm1020"

		"arm,arm1020e"

		"arm,arm1022"

		"arm,arm1026"

		"arm,arm720"

		"arm,arm740"

		"arm,arm7tdmi"

		"arm,arm920"

		"arm,arm922"

		"arm,arm925"

		"arm,arm926"

		"arm,arm940"

		"arm,arm946"

		"arm,arm9tdmi"

		"arm,cortex-a5"

		"arm,cortex-a7"

		"arm,cortex-a8"

		"arm,cortex-a9"

		"arm,cortex-a15"

		"arm,arm1136"

		"arm,arm1156"

		"arm,arm1176"

		"arm,arm11mpcore"

		"faraday,fa526"

		"intel,sa110"

		"intel,sa1100"

		"marvell,feroceon"

		"marvell,mohawk"

		"marvell,xsc3"

		"marvell,xscale"



Example:



	cpus {

		#size-cells = <0>;

		#address-cells = <1>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0x0>;

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0x1>;

		};



		CPU2: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x100>;

		};



		CPU3: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x101>;

		};

	};

arch/arm/Kconfig

+3 −1
Original line number Diff line number Diff line
@@ -5,8 +5,9 @@ config ARM 
	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE

	select ARCH_HAVE_CUSTOM_GPIO_H

	select ARCH_WANT_IPC_PARSE_VERSION

	select BUILDTIME_EXTABLE_SORT if MMU

	select CPU_PM if (SUSPEND || CPU_IDLE)

	select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN

	select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU

	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)

	select GENERIC_CLOCKEVENTS_BROADCAST if SMP

	select GENERIC_IRQ_PROBE
@@ -21,6 +22,7 @@ config ARM 
	select HAVE_AOUT

	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL

	select HAVE_ARCH_KGDB

	select HAVE_ARCH_SECCOMP_FILTER

	select HAVE_ARCH_TRACEHOOK

	select HAVE_BPF_JIT

	select HAVE_C_RECORDMCOUNT

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ KBUILD_DEFCONFIG := versatile_defconfig 
# defines filename extension depending memory management type.

ifeq ($(CONFIG_MMU),)

MMUEXT		:= -nommu

KBUILD_CFLAGS	+= $(call cc-option,-mno-unaligned-access)

endif



ifeq ($(CONFIG_FRAME_POINTER),y)

arch/arm/common/gic.c

+36 −9
Original line number Diff line number Diff line
@@ -69,6 +69,14 @@ struct gic_chip_data { 


static DEFINE_RAW_SPINLOCK(irq_controller_lock);



/*

 * The GIC mapping of CPU interfaces does not necessarily match

 * the logical CPU numbering.  Let's use a mapping as returned

 * by the GIC itself.

 */

#define NR_GIC_CPU_IF 8

static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;



/*

 * Supported arch specific GIC irq extension.

 * Default make them NULL.
@@ -238,11 +246,11 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 
	unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);

	u32 val, mask, bit;



	if (cpu >= 8 || cpu >= nr_cpu_ids)

	if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)

		return -EINVAL;



	mask = 0xff << shift;

	bit = 1 << (cpu_logical_map(cpu) + shift);

	bit = gic_cpu_map[cpu] << shift;



	raw_spin_lock(&irq_controller_lock);

	val = readl_relaxed(reg) & ~mask;
@@ -349,11 +357,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic) 
	u32 cpumask;

	unsigned int gic_irqs = gic->gic_irqs;

	void __iomem *base = gic_data_dist_base(gic);

	u32 cpu = cpu_logical_map(smp_processor_id());



	cpumask = 1 << cpu;

	cpumask |= cpumask << 8;

	cpumask |= cpumask << 16;



	writel_relaxed(0, base + GIC_DIST_CTRL);
@@ -366,6 +369,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) 
	/*

	 * Set all global interrupts to this CPU only.

	 */

	cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);

	for (i = 32; i < gic_irqs; i += 4)

		writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
@@ -389,8 +393,24 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) 
{

	void __iomem *dist_base = gic_data_dist_base(gic);

	void __iomem *base = gic_data_cpu_base(gic);

	unsigned int cpu_mask, cpu = smp_processor_id();

	int i;



	/*

	 * Get what the GIC says our CPU mask is.

	 */

	BUG_ON(cpu >= NR_GIC_CPU_IF);

	cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);

	gic_cpu_map[cpu] = cpu_mask;



	/*

	 * Clear our mask from the other map entries in case they're

	 * still undefined.

	 */

	for (i = 0; i < NR_GIC_CPU_IF; i++)

		if (i != cpu)

			gic_cpu_map[i] &= ~cpu_mask;



	/*

	 * Deal with the banked PPI and SGI interrupts - disable all

	 * PPI interrupts, ensure all SGI interrupts are enabled.
@@ -646,7 +666,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, 
{

	irq_hw_number_t hwirq_base;

	struct gic_chip_data *gic;

	int gic_irqs, irq_base;

	int gic_irqs, irq_base, i;



	BUG_ON(gic_nr >= MAX_GIC_NR);
@@ -682,6 +702,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, 
		gic_set_base_accessor(gic, gic_get_common_base);

	}



	/*

	 * Initialize the CPU interface map to all CPUs.

	 * It will be refined as each CPU probes its ID.

	 */

	for (i = 0; i < NR_GIC_CPU_IF; i++)

		gic_cpu_map[i] = 0xff;



	/*

	 * For primary GICs, skip over SGIs.

	 * For secondary GICs, skip over PPIs, too.
@@ -737,7 +764,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 


	/* Convert our logical CPU mask into a physical one. */

	for_each_cpu(cpu, mask)

		map |= 1 << cpu_logical_map(cpu);

		map |= gic_cpu_map[cpu];



	/*

	 * Ensure that stores to Normal memory are visible to the

arch/arm/common/vic.c

+6 −13
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq, 
	v->resume_sources = resume_sources;

	v->irq = irq;

	vic_id++;

	v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0,

	v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,

					  &vic_irqdomain_ops, v);

}
@@ -350,7 +350,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, 
	vic_register(base, irq_start, vic_sources, 0, node);

}



void __init __vic_init(void __iomem *base, unsigned int irq_start,

void __init __vic_init(void __iomem *base, int irq_start,

			      u32 vic_sources, u32 resume_sources,

			      struct device_node *node)

{
@@ -407,7 +407,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, 
int __init vic_of_init(struct device_node *node, struct device_node *parent)

{

	void __iomem *regs;

	int irq_base;



	if (WARN(parent, "non-root VICs are not supported"))

		return -EINVAL;
@@ -416,18 +415,12 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent) 
	if (WARN_ON(!regs))

		return -EIO;



	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());

	if (WARN_ON(irq_base < 0))

		goto out_unmap;



	__vic_init(regs, irq_base, ~0, ~0, node);

	/*

	 * Passing -1 as first IRQ makes the simple domain allocate descriptors

	 */

	__vic_init(regs, -1, ~0, ~0, node);



	return 0;



 out_unmap:

	iounmap(regs);



	return -EIO;

}

#endif /* CONFIG OF */

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