Commit b0f82b81 authored by Frederic Weisbecker's avatar Frederic Weisbecker
Browse files

perf: Drop the skip argument from perf_arch_fetch_regs_caller 



Drop this argument now that we always want to rewind only to the
state of the first caller.
It means frame pointers are not necessary anymore to reliably get
the source of an event. But this also means we need this helper
to be a macro now, as an inline function is not an option since
we need to know when to provide a default implentation.

Signed-off-by: default avatarFrederic Weisbecker <fweisbec@gmail.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Cc: David Miller <davem@davemloft.net>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
parent c9cf4dbb

arch/powerpc/include/asm/perf_event.h

+12 −0
Original line number Diff line number Diff line
@@ -21,3 +21,15 @@ 
#ifdef CONFIG_FSL_EMB_PERF_EVENT

#include <asm/perf_event_fsl_emb.h>

#endif



#ifdef CONFIG_PERF_EVENTS

#include <asm/ptrace.h>

#include <asm/reg.h>



#define perf_arch_fetch_caller_regs(regs, __ip)			\

	do {							\

		(regs)->nip = __ip;				\

		(regs)->gpr[1] = *(unsigned long *)__get_SP();	\

		asm volatile("mfmsr %0" : "=r" ((regs)->msr));	\

	} while (0)

#endif

arch/powerpc/kernel/misc.S

+0 −26
Original line number Diff line number Diff line
@@ -127,29 +127,3 @@ _GLOBAL(__setup_cpu_power7) 
_GLOBAL(__restore_cpu_power7)

	/* place holder */

	blr
 


/*

 * Get a minimal set of registers for our caller's nth caller.

 * r3 = regs pointer, r5 = n.

 *

 * We only get R1 (stack pointer), NIP (next instruction pointer)

 * and LR (link register).  These are all we can get in the

 * general case without doing complicated stack unwinding, but

 * fortunately they are enough to do a stack backtrace, which

 * is all we need them for.

 */

_GLOBAL(perf_arch_fetch_caller_regs)

	mr	r6,r1

	cmpwi	r5,0

	mflr	r4

	ble	2f

	mtctr	r5

1:	PPC_LL	r6,0(r6)

	bdnz	1b

	PPC_LL	r4,PPC_LR_STKOFF(r6)

2:	PPC_LL	r7,0(r6)

	PPC_LL	r7,PPC_LR_STKOFF(r7)

	PPC_STL	r6,GPR1-STACK_FRAME_OVERHEAD(r3)

	PPC_STL	r4,_NIP-STACK_FRAME_OVERHEAD(r3)

	PPC_STL	r7,_LINK-STACK_FRAME_OVERHEAD(r3)

	blr

arch/sparc/include/asm/perf_event.h

+8 −0
Original line number Diff line number Diff line
@@ -6,7 +6,15 @@ extern void set_perf_event_pending(void); 
#define	PERF_EVENT_INDEX_OFFSET	0



#ifdef CONFIG_PERF_EVENTS

#include <asm/ptrace.h>



extern void init_hw_perf_events(void);



extern void

__perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip);



#define perf_arch_fetch_caller_regs(pt_regs, ip)	\

	__perf_arch_fetch_caller_regs(pt_regs, ip, 1);

#else

static inline void init_hw_perf_events(void)	{ }

#endif

arch/sparc/kernel/helpers.S

+3 −3
Original line number Diff line number Diff line
@@ -47,9 +47,9 @@ stack_trace_flush: 
	.size		stack_trace_flush,.-stack_trace_flush



#ifdef CONFIG_PERF_EVENTS

	.globl		perf_arch_fetch_caller_regs

	.type		perf_arch_fetch_caller_regs,#function

perf_arch_fetch_caller_regs:

	.globl		__perf_arch_fetch_caller_regs

	.type		__perf_arch_fetch_caller_regs,#function

__perf_arch_fetch_caller_regs:

	/* We always read the %pstate into %o5 since we will use

	 * that to construct a fake %tstate to store into the regs.

	 */

arch/x86/include/asm/perf_event.h

+13 −0
Original line number Diff line number Diff line
@@ -140,6 +140,19 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 
extern unsigned long perf_misc_flags(struct pt_regs *regs);

#define perf_misc_flags(regs)	perf_misc_flags(regs)



#include <asm/stacktrace.h>



/*

 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags

 * and the comment with PERF_EFLAGS_EXACT.

 */

#define perf_arch_fetch_caller_regs(regs, __ip)		{	\

	(regs)->ip = (__ip);					\

	(regs)->bp = caller_frame_pointer();			\

	(regs)->cs = __KERNEL_CS;				\

	regs->flags = 0;					\

}



#else

static inline void init_hw_perf_events(void)		{ }

static inline void perf_events_lapic_init(void)	{ }

CRA Git | Maintained and supported by SUSTech CRA and CCSE