Commit b0b6f0dd authored by Alex Elder's avatar Alex Elder Committed by Jakub Kicinski
Browse files

net: ipa: update gsi registers for IPA v4.5 



Very few GSI register definitions change for IPA v4.5, however
as a group their position in memory shifts a constant amount
(handled by the next commit).

Add definitions and update comments to the set of GSI registers to
support changes that come with IPA v4.5.

Update the logic in gsi_channel_program() to accommodate the new
(expanded) PREFETCH_MODE field in the CH_C_QOS register.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 8bfc4e21

drivers/net/ipa/gsi.c

+8 −2
Original line number Diff line number Diff line
@@ -784,8 +784,14 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell) 
	/* v4.0 introduces an escape buffer for prefetch.  We use it

	 * on all but the AP command channel.

	 */

	if (gsi->version != IPA_VERSION_3_5_1 && !channel->command)

	if (gsi->version != IPA_VERSION_3_5_1 && !channel->command) {

		/* If not otherwise set, prefetch buffers are used */

		if (gsi->version < IPA_VERSION_4_5)

			val |= USE_ESCAPE_BUF_ONLY_FMASK;

		else

			val |= u32_encode_bits(GSI_ESCAPE_BUF_ONLY,

					       PREFETCH_MODE_FMASK);

	}



	iowrite32(val, gsi->virt + GSI_CH_C_QOS_OFFSET(channel_id));

drivers/net/ipa/gsi_reg.h

+13 −0
Original line number Diff line number Diff line
@@ -105,6 +105,16 @@ enum gsi_channel_type { 
#define USE_DB_ENG_FMASK		GENMASK(9, 9)

/* The next field is only present for IPA v4.0, v4.1, and v4.2 */

#define USE_ESCAPE_BUF_ONLY_FMASK	GENMASK(10, 10)

/* The next two fields are present for IPA v4.5 and above */

#define PREFETCH_MODE_FMASK		GENMASK(13, 10)

#define EMPTY_LVL_THRSHOLD_FMASK	GENMASK(23, 16)

/** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */

enum gsi_prefetch_mode {

	GSI_USE_PREFETCH_BUFS			= 0x0,

	GSI_ESCAPE_BUF_ONLY			= 0x1,

	GSI_SMART_PREFETCH			= 0x2,

	GSI_FREE_PREFETCH			= 0x3,

};



#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \

		GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP)
@@ -287,6 +297,9 @@ enum gsi_iram_size { 
/* The next two values are available for IPA v4.0 and above */

	IRAM_SIZE_TWO_N_HALF_KB			= 0x2,

	IRAM_SIZE_THREE_KB			= 0x3,

	/* The next two values are available for IPA v4.5 and above */

	IRAM_SIZE_THREE_N_HALF_KB		= 0x4,

	IRAM_SIZE_FOUR_KB			= 0x5,

};



/* IRQ condition for each type is cleared by writing type-specific register */

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