Commit b0b651ae authored Dec 09, 2019 by Thierry Reding Committed by Ben Skeggs Jan 15, 2020

drm/nouveau/tegra: Avoid pulsing reset twice



When the GPU powergate is controlled by a generic power domain provider,
the reset will automatically be asserted and deasserted as part of the
power-ungating procedure.

On some Jetson TX2 boards, doing an additional assert and deassert of
the GPU outside of the power-ungate procedure can cause the GPU to go
into a bad state where the memory interface can no longer access system
memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

parent f1331ea8

drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -52,18 +52,18 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
		clk_set_rate(tdev->clk_pwr, 204000000);
		udelay(10);

		if (!tdev->pdev->dev.pm_domain) {
		reset_control_assert(tdev->rst);
		udelay(10);

		if (!tdev->pdev->dev.pm_domain) {
		ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
		if (ret)
		goto err_clamp;
		udelay(10);
		}

		reset_control_deassert(tdev->rst);
		udelay(10);
		}

		return 0;

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