Commit b096c137 authored by Emilio López's avatar Emilio López Committed by Vinod Koul
Browse files

dmaengine: sun4i: Add support for the DMA engine on sun[457]i SoCs 



This patch adds support for the DMA engine present on Allwinner A10,
A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
and dedicated. The main difference is in the mode of operation;
while a single normal channel may be operating at any given time,
dedicated channels may operate simultaneously provided there is no
overlap of source or destination.

Hardware documentation can be found on A10 User Manual (section 12), A13
User Manual (section 14) and A20 User Manual (section 1.12)

Signed-off-by: default avatarEmilio López <emilio@elopez.com.ar>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 77757291

Documentation/devicetree/bindings/dma/sun4i-dma.txt

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Allwinner A10 DMA Controller



This driver follows the generic DMA bindings defined in dma.txt.



Required properties:



- compatible:	Must be "allwinner,sun4i-a10-dma"

- reg:		Should contain the registers base address and length

- interrupts:	Should contain a reference to the interrupt used by this device

- clocks:	Should contain a reference to the parent AHB clock

- #dma-cells :	Should be 2, first cell denoting normal or dedicated dma,

		second cell holding the request line number.



Example:

	dma: dma-controller@01c02000 {

		compatible = "allwinner,sun4i-a10-dma";

		reg = <0x01c02000 0x1000>;

		interrupts = <27>;

		clocks = <&ahb_gates 6>;

		#dma-cells = <2>;

	};



Clients:



DMA clients connected to the Allwinner A10 DMA controller must use the

format described in the dma.txt file, using a three-cell specifier for

each channel: a phandle plus two integer cells.

The three cells in order are:



1. A phandle pointing to the DMA controller.

2. Whether it is using normal (0) or dedicated (1) channels

3. The port ID as specified in the datasheet



Example:

	spi2: spi@01c17000 {

		compatible = "allwinner,sun4i-a10-spi";

		reg = <0x01c17000 0x1000>;

		interrupts = <0 12 4>;

		clocks = <&ahb_gates 22>, <&spi2_clk>;

		clock-names = "ahb", "mod";

		dmas = <&dma 1 29>, <&dma 1 28>;

		dma-names = "rx", "tx";

		status = "disabled";

		#address-cells = <1>;

		#size-cells = <0>;

	};

drivers/dma/Kconfig

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@@ -434,6 +434,17 @@ config XILINX_VDMA 
	  channels, Memory Mapped to Stream (MM2S) and Stream to

	  channels, Memory Mapped to Stream (MM2S) and Stream to

	  Memory Mapped (S2MM) for the data transfers.

	  Memory Mapped (S2MM) for the data transfers.





config DMA_SUN4I

	tristate "Allwinner A10 DMA SoCs support"

	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || COMPILE_TEST

	default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)

	select DMA_ENGINE

	select DMA_OF

	select DMA_VIRTUAL_CHANNELS

	help

	  Enable support for the DMA controller present in the sun4i,

	  sun5i and sun7i Allwinner ARM SoCs.



config DMA_SUN6I

config DMA_SUN6I

	tristate "Allwinner A31 SoCs DMA support"

	tristate "Allwinner A31 SoCs DMA support"

	depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST

	depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST

drivers/dma/Makefile

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@@ -55,5 +55,6 @@ obj-y += xilinx/ 
obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o

obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o

obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o

obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o

obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o

obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o

obj-$(CONFIG_DMA_SUN4I) += sun4i-dma.o

obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o

obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o

obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
 
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o

drivers/dma/sun4i-dma.c

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