Commit b08ac66b authored Mar 18, 2014 by Viller Hsiao Committed by Ralf Baechle Mar 19, 2014

MIPS: ftrace: Tweak safe_load()/safe_store() macros



Due to name collision in ftrace safe_load and safe_store macros,
these macros cannot take expressions as operands.

For example, compiler will complain for a macro call like the following:
  safe_store_code(new_code2, ip + 4, faulted);

  arch/mips/include/asm/ftrace.h:61:6: note: in definition of macro 'safe_store'
     : [dst] "r" (dst), [src] "r" (src)\
        ^
  arch/mips/kernel/ftrace.c:118:2: note: in expansion of macro 'safe_store_code'
    safe_store_code(new_code2, ip + 4, faulted);
    ^
  arch/mips/kernel/ftrace.c:118:32: error: undefined named operand 'ip + 4'
    safe_store_code(new_code2, ip + 4, faulted);
                                  ^
  arch/mips/include/asm/ftrace.h:61:6: note: in definition of macro 'safe_store'
     : [dst] "r" (dst), [src] "r" (src)\
        ^
  arch/mips/kernel/ftrace.c:118:2: note: in expansion of macro 'safe_store_code'
    safe_store_code(new_code2, ip + 4, faulted);
    ^

This build error is triggered by a4671094 [MIPS: ftrace: Fix icache flush
range error].  Tweak variable naming in those macros to allow flexible
operands.

Signed-off-by: Viller Hsiao <villerhsiao@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: rostedt@goodmis.org
Cc: fweisbec@gmail.com
Cc: mingo@redhat.com
Cc: Qais.Yousef@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/6622/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 4fe2169a

arch/mips/include/asm/ftrace.h

+10 −10

Original line number	Diff line number	Diff line
		@@ -22,12 +22,12 @@ extern void _mcount(void);
		#define safe_load(load, src, dst, error) \
		do { \
		asm volatile ( \
		"1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
		" li %[" STR(error) "], 0\n" \
		"1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
		" li %[tmp_err], 0\n" \
		"2:\n" \
		\
		".section .fixup, \"ax\"\n" \
		"3: li %[" STR(error) "], 1\n" \
		"3: li %[tmp_err], 1\n" \
		" j 2b\n" \
		".previous\n" \
		\
		@@ -35,8 +35,8 @@ do { \
		STR(PTR) "\t1b, 3b\n\t" \
		".previous\n" \
		\
		: [dst] "=&r" (dst), [error] "=r" (error)\
		: [src] "r" (src) \
		: [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
		: [tmp_src] "r" (src) \
		: "memory" \
		); \
		} while (0)
		@@ -44,12 +44,12 @@ do { \
		#define safe_store(store, src, dst, error) \
		do { \
		asm volatile ( \
		"1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
		" li %[" STR(error) "], 0\n" \
		"1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
		" li %[tmp_err], 0\n" \
		"2:\n" \
		\
		".section .fixup, \"ax\"\n" \
		"3: li %[" STR(error) "], 1\n" \
		"3: li %[tmp_err], 1\n" \
		" j 2b\n" \
		".previous\n" \
		\
		@@ -57,8 +57,8 @@ do { \
		STR(PTR) "\t1b, 3b\n\t" \
		".previous\n" \
		\
		: [error] "=r" (error) \
		: [dst] "r" (dst), [src] "r" (src)\
		: [tmp_err] "=r" (error) \
		: [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
		: "memory" \
		); \
		} while (0)

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