Commit b068a860 authored by James Ausmus's avatar James Ausmus Committed by Lucas De Marchi
Browse files

drm/i915: Move SAGV block time to dev_priv 



In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.

v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)

v3: Change sagv_block_time_us to u32 (Lucas), Change fallback value to
-1 (Lucas), use intel_has_sagv for setup check rather than hand-rolling
(Lucas)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarJames Ausmus <james.ausmus@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191004221449.1317-1-james.ausmus@intel.com
Link: https://patchwork.freedesktop.org/patch/msgid/20191009172315.11004-1-lucas.demarchi@intel.com
parent 52111c46

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1267,6 +1267,8 @@ struct drm_i915_private { 
		I915_SAGV_NOT_CONTROLLED

	} sagv_status;



	u32 sagv_block_time_us;



	struct {

		/*

		 * Raw watermark latency values:

drivers/gpu/drm/i915/intel_pm.c

+24 −9
Original line number Diff line number Diff line
@@ -3638,6 +3638,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv) 
		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;

}



static void

skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)

{

	if (IS_GEN(dev_priv, 11)) {

		dev_priv->sagv_block_time_us = 10;

		return;

	} else if (IS_GEN(dev_priv, 10)) {

		dev_priv->sagv_block_time_us = 20;

		return;

	} else if (IS_GEN(dev_priv, 9)) {

		dev_priv->sagv_block_time_us = 30;

		return;

	} else {

		MISSING_CASE(INTEL_GEN(dev_priv));

	}



	/* Default to an unusable block time */

	dev_priv->sagv_block_time_us = -1;

}



/*

 * SAGV dynamically adjusts the system agent voltage and clock frequencies

 * depending on power and performance requirements. The display engine access
@@ -3726,18 +3746,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) 
	struct intel_crtc_state *crtc_state;

	enum pipe pipe;

	int level, latency;

	int sagv_block_time_us;



	if (!intel_has_sagv(dev_priv))

		return false;



	if (IS_GEN(dev_priv, 9))

		sagv_block_time_us = 30;

	else if (IS_GEN(dev_priv, 10))

		sagv_block_time_us = 20;

	else

		sagv_block_time_us = 10;



	/*

	 * If there are no active CRTCs, no additional checks need be performed

	 */
@@ -3784,7 +3796,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) 
		 * incur memory latencies higher than sagv_block_time_us we

		 * can't enable SAGV.

		 */

		if (latency < sagv_block_time_us)

		if (latency < dev_priv->sagv_block_time_us)

			return false;

	}
@@ -8985,6 +8997,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv) 
	else if (IS_GEN(dev_priv, 5))

		i915_ironlake_get_mem_freq(dev_priv);



	if (intel_has_sagv(dev_priv))

		skl_setup_sagv_block_time(dev_priv);



	/* For FIFO watermark updates */

	if (INTEL_GEN(dev_priv) >= 9) {

		skl_setup_wm_latency(dev_priv);

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