Commit b0504e39 authored by Michal Simek's avatar Michal Simek
Browse files

ARM: zynq: Map I/O memory on clkc init 



The clkc has its registers in the range of the slcr.
Instead of passing around the slcr base address pointer, let the clkc get the
address from the DT.
This prepares the slcr to be a real driver with multiple memory ranges
(slcr, clocks, pinctrl,...)

Signed-off-by: default avatarSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 5e218280

Documentation/devicetree/bindings/clock/zynq-7000.txt

+3 −1
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ for all clock consumers of PS clocks. 
Required properties:

 - #clock-cells : Must be 1

 - compatible : "xlnx,ps7-clkc"

 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >

 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ

		      (usually 33 MHz oscillators are used for Zynq platforms)

 - clock-output-names : List of strings used to name the clock outputs. Shall be
@@ -87,10 +88,11 @@ Clock outputs: 
 47: dbg_apb



Example:

	clkc: clkc {

	clkc: clkc@100 {

		#clock-cells = <1>;

		compatible = "xlnx,ps7-clkc";

		ps-clk-frequency = <33333333>;

		reg = <0x100 0x100>;

		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",

				"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",

				"dci", "lqspi", "smc", "pcap", "gem0", "gem1",

arch/arm/boot/dts/zynq-7000.dtsi

+20 −22
Original line number Diff line number Diff line
@@ -123,14 +123,12 @@ 
		} ;



		slcr: slcr@f8000000 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "xlnx,zynq-slcr", "syscon";

			reg = <0xF8000000 0x1000>;



			clocks {

				#address-cells = <1>;

				#size-cells = <0>;



				clkc: clkc {

			ranges;

			clkc: clkc@100 {

				#clock-cells = <1>;

				compatible = "xlnx,ps7-clkc";

				ps-clk-frequency = <33333333>;
@@ -146,7 +144,7 @@ 
						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",

						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",

						"dbg_trc", "dbg_apb";

				};

				reg = <0x100 0x100>;

			};

		};

arch/arm/mach-zynq/common.c

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ static void __init zynq_timer_init(void) 
{

	zynq_early_slcr_init();



	zynq_clock_init(zynq_slcr_base);

	zynq_clock_init();

	clocksource_of_init();

}

drivers/clk/zynq/clkc.c

+63 −26
Original line number Diff line number Diff line
@@ -21,34 +21,35 @@ 
#include <linux/clk/zynq.h>

#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/slab.h>

#include <linux/string.h>

#include <linux/io.h>



static void __iomem *zynq_slcr_base_priv;



#define SLCR_ARMPLL_CTRL		(zynq_slcr_base_priv + 0x100)

#define SLCR_DDRPLL_CTRL		(zynq_slcr_base_priv + 0x104)

#define SLCR_IOPLL_CTRL			(zynq_slcr_base_priv + 0x108)

#define SLCR_PLL_STATUS			(zynq_slcr_base_priv + 0x10c)

#define SLCR_ARM_CLK_CTRL		(zynq_slcr_base_priv + 0x120)

#define SLCR_DDR_CLK_CTRL		(zynq_slcr_base_priv + 0x124)

#define SLCR_DCI_CLK_CTRL		(zynq_slcr_base_priv + 0x128)

#define SLCR_APER_CLK_CTRL		(zynq_slcr_base_priv + 0x12c)

#define SLCR_GEM0_CLK_CTRL		(zynq_slcr_base_priv + 0x140)

#define SLCR_GEM1_CLK_CTRL		(zynq_slcr_base_priv + 0x144)

#define SLCR_SMC_CLK_CTRL		(zynq_slcr_base_priv + 0x148)

#define SLCR_LQSPI_CLK_CTRL		(zynq_slcr_base_priv + 0x14c)

#define SLCR_SDIO_CLK_CTRL		(zynq_slcr_base_priv + 0x150)

#define SLCR_UART_CLK_CTRL		(zynq_slcr_base_priv + 0x154)

#define SLCR_SPI_CLK_CTRL		(zynq_slcr_base_priv + 0x158)

#define SLCR_CAN_CLK_CTRL		(zynq_slcr_base_priv + 0x15c)

#define SLCR_CAN_MIOCLK_CTRL		(zynq_slcr_base_priv + 0x160)

#define SLCR_DBG_CLK_CTRL		(zynq_slcr_base_priv + 0x164)

#define SLCR_PCAP_CLK_CTRL		(zynq_slcr_base_priv + 0x168)

#define SLCR_FPGA0_CLK_CTRL		(zynq_slcr_base_priv + 0x170)

#define SLCR_621_TRUE			(zynq_slcr_base_priv + 0x1c4)

#define SLCR_SWDT_CLK_SEL		(zynq_slcr_base_priv + 0x304)

static void __iomem *zynq_clkc_base;



#define SLCR_ARMPLL_CTRL		(zynq_clkc_base + 0x00)

#define SLCR_DDRPLL_CTRL		(zynq_clkc_base + 0x04)

#define SLCR_IOPLL_CTRL			(zynq_clkc_base + 0x08)

#define SLCR_PLL_STATUS			(zynq_clkc_base + 0x0c)

#define SLCR_ARM_CLK_CTRL		(zynq_clkc_base + 0x20)

#define SLCR_DDR_CLK_CTRL		(zynq_clkc_base + 0x24)

#define SLCR_DCI_CLK_CTRL		(zynq_clkc_base + 0x28)

#define SLCR_APER_CLK_CTRL		(zynq_clkc_base + 0x2c)

#define SLCR_GEM0_CLK_CTRL		(zynq_clkc_base + 0x40)

#define SLCR_GEM1_CLK_CTRL		(zynq_clkc_base + 0x44)

#define SLCR_SMC_CLK_CTRL		(zynq_clkc_base + 0x48)

#define SLCR_LQSPI_CLK_CTRL		(zynq_clkc_base + 0x4c)

#define SLCR_SDIO_CLK_CTRL		(zynq_clkc_base + 0x50)

#define SLCR_UART_CLK_CTRL		(zynq_clkc_base + 0x54)

#define SLCR_SPI_CLK_CTRL		(zynq_clkc_base + 0x58)

#define SLCR_CAN_CLK_CTRL		(zynq_clkc_base + 0x5c)

#define SLCR_CAN_MIOCLK_CTRL		(zynq_clkc_base + 0x60)

#define SLCR_DBG_CLK_CTRL		(zynq_clkc_base + 0x64)

#define SLCR_PCAP_CLK_CTRL		(zynq_clkc_base + 0x68)

#define SLCR_FPGA0_CLK_CTRL		(zynq_clkc_base + 0x70)

#define SLCR_621_TRUE			(zynq_clkc_base + 0xc4)

#define SLCR_SWDT_CLK_SEL		(zynq_clkc_base + 0x204)



#define NUM_MIO_PINS	54
@@ -569,8 +570,44 @@ static void __init zynq_clk_setup(struct device_node *np) 


CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);



void __init zynq_clock_init(void __iomem *slcr_base)

void __init zynq_clock_init(void)

{

	zynq_slcr_base_priv = slcr_base;

	struct device_node *np;

	struct device_node *slcr;

	struct resource res;



	np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");

	if (!np) {

		pr_err("%s: clkc node not found\n", __func__);

		goto np_err;

	}



	if (of_address_to_resource(np, 0, &res)) {

		pr_err("%s: failed to get resource\n", np->name);

		goto np_err;

	}



	slcr = of_get_parent(np);



	if (slcr->data) {

		zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;

	} else {

		pr_err("%s: Unable to get I/O memory\n", np->name);

		of_node_put(slcr);

		goto np_err;

	}



	pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);



	of_node_put(slcr);

	of_node_put(np);



	of_clk_init(NULL);



	return;



np_err:

	of_node_put(np);

	BUG();

	return;

}

include/linux/clk/zynq.h

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 


#include <linux/spinlock.h>



void zynq_clock_init(void __iomem *slcr);

void zynq_clock_init(void);



struct clk *clk_register_zynq_pll(const char *name, const char *parent,

		void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,

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