Commit b02d4081 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: refine cz uvd clock gate logic. 



sw clockgate was used on uvd6.0.
when uvd is idle, we gate the uvd clock.
when decode, we ungate the uvd clock.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 58a6a7dd

drivers/gpu/drm/amd/amdgpu/cz_dpm.c

+2 −4
Original line number Diff line number Diff line
@@ -2111,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) 


	if (gate) {

		if (pi->caps_uvd_pg) {

			/* disable clockgating so we can properly shut down the block */

			ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

							    AMD_CG_STATE_UNGATE);

							    AMD_CG_STATE_GATE);

			if (ret) {

				DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");

				return;
@@ -2159,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) 
				return;

			}



			/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */

			ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,

							    AMD_CG_STATE_GATE);

							    AMD_CG_STATE_UNGATE);

			if (ret) {

				DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");

				return;

drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c

+2 −2
Original line number Diff line number Diff line
@@ -169,7 +169,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 
	if (bgate) {

		cgs_set_clockgating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_CG_STATE_UNGATE);

						AMD_CG_STATE_GATE);

		cgs_set_powergating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_PG_STATE_GATE);
@@ -182,7 +182,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 
						AMD_CG_STATE_UNGATE);

		cgs_set_clockgating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_PG_STATE_GATE);

						AMD_PG_STATE_UNGATE);

		cz_dpm_update_uvd_dpm(hwmgr, false);

	}

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