Commit afff455c authored by Andrew Bresticker's avatar Andrew Bresticker Committed by Thierry Reding
Browse files

clk: tegra: pll: Fix issues with rates for VCO PLLs 



Without this change clk_get_rate would return the final output
rather than the VCO output as it would factor in the pdiv when
it shouldn't. This will cause problems for all dividers in the
subtree of the VCO PLL.

Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Reviewed-by: default avatarBenson Leung <bleung@chromium.org>
Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 6b301a05

drivers/clk/tegra/clk-pll.c

+12 −4
Original line number Diff line number Diff line
@@ -752,6 +752,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
		spin_lock_irqsave(pll->lock, flags);



	_get_pll_mnp(pll, &old_cfg);

	if (pll->params->flags & TEGRA_PLL_VCO_OUT)

		cfg.p = old_cfg.p;



	if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||

		old_cfg.sdm_data != cfg.sdm_data)
@@ -812,12 +814,16 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 


	_get_pll_mnp(pll, &cfg);



	if (pll->params->flags & TEGRA_PLL_VCO_OUT) {

		pdiv = 1;

	} else {

		pdiv = _hw_to_p_div(hw, cfg.p);

		if (pdiv < 0) {

			WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",

			__clk_get_name(hw->clk), cfg.p);

			     clk_hw_get_name(hw), cfg.p);

			pdiv = 1;

		}

	}



	if (pll->params->set_gain)

		pll->params->set_gain(&cfg);
@@ -1103,6 +1109,8 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 
		spin_lock_irqsave(pll->lock, flags);



	_get_pll_mnp(pll, &old_cfg);

	if (pll->params->flags & TEGRA_PLL_VCO_OUT)

		cfg.p = old_cfg.p;



	if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)

		ret = _program_pll(hw, &cfg, rate);

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