Commit afd55e6d authored by Sivaprakash Murugesan's avatar Sivaprakash Murugesan Committed by Vinod Koul
Browse files

phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init 



There were some problem in ipq8074 Gen2 PCIe phy init sequence.

1. Few register values were wrongly updated in the phy init sequence.
2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter
   register which is added in serdes table causing the wrong register
   was getting updated.
3. Clocks and resets were not added in the phy init.

Fix these to make Gen2 PCIe port on ipq8074 devices to work.

Fixes: eef243d0 ("phy: qcom-qmp: Add support for IPQ8074")
Cc: stable@vger.kernel.org
Co-developed-by: default avatarSelvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: default avatarSelvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1596036607-11877-4-git-send-email-sivaprak@codeaurora.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 04db2304

drivers/phy/qualcomm/phy-qcom-qmp.c

+9 −7
Original line number Diff line number Diff line
@@ -604,8 +604,8 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),

	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
@@ -631,7 +631,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
@@ -640,7 +639,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),

	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),

};



static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
@@ -648,6 +646,8 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),

	QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),

	QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),

};



static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
@@ -658,7 +658,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),

	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),

	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),

	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),

};



static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
@@ -2046,6 +2045,9 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 
	.pwrdn_ctrl		= SW_PWRDN,

};



static const char * const ipq8074_pciephy_clk_l[] = {

	"aux", "cfg_ahb",

};

/* list of resets */

static const char * const ipq8074_pciephy_reset_l[] = {

	"phy", "common",
@@ -2063,8 +2065,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 
	.rx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_rx_tbl),

	.pcs_tbl		= ipq8074_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_pcie_pcs_tbl),

	.clk_list		= NULL,

	.num_clks		= 0,

	.clk_list		= ipq8074_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),

	.reset_list		= ipq8074_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),

	.vreg_list		= NULL,

drivers/phy/qualcomm/phy-qcom-qmp.h

+2 −0
Original line number Diff line number Diff line
@@ -77,6 +77,8 @@ 
#define QSERDES_COM_CORECLK_DIV_MODE1			0x1bc



/* Only for QMP V2 PHY - TX registers */

#define QSERDES_TX_EMP_POST1_LVL			0x018

#define QSERDES_TX_SLEW_CNTL				0x040

#define QSERDES_TX_RES_CODE_LANE_OFFSET			0x054

#define QSERDES_TX_DEBUG_BUS_SEL			0x064

#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN	0x068

CRA Git | Maintained and supported by SUSTech CRA and CCSE