Merge tag 'qcom-arm64-for-4.19-2' of...

== Introduction==

LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,

that can be shared by multiple clients. Clients here are different cores in the

SOC, the idea is to minimize the local caches at the clients and migrate to

common pool of memory. Cache memory is divided into partitions called slices

which are assigned to clients. Clients can query the slice details, activate

and deactivate them.

Properties:

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,sdm845-llcc"

- reg:

	Usage: required

	Value Type: <prop-encoded-array>

	Definition: Start address and the the size of the register region.

Example:

	cache-controller@1100000 {

		compatible = "qcom,sdm845-llcc";

		reg = <0x1100000 0x250000>;

	};

RPMH RSC:

------------

Resource Power Manager Hardened (RPMH) is the mechanism for communicating with

the hardened resource accelerators on Qualcomm SoCs. Requests to the resources

can be written to the Trigger Command Set (TCS)  registers and using a (addr,

val) pair and triggered. Messages in the TCS are then sent in sequence over an

internal bus.

The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity

(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and

active/wake resource requests. Multiple such DRVs can exist in a SoC and can

be written to from Linux. The structure of each DRV follows the same template

with a few variations that are captured by the properties here.

A TCS may be triggered from Linux or triggered by the F/W after all the CPUs

have powered off to facilitate idle power saving. TCS could be classified as -

	ACTIVE  /* Triggered by Linux */

	SLEEP   /* Triggered by F/W */

	WAKE    /* Triggered by F/W */

	CONTROL /* Triggered by F/W */

The order in which they are described in the DT, should match the hardware

configuration.

Requests can be made for the state of a resource, when the subsystem is active

or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state

will be an aggregate of the sleep votes from each of those subsystems. Clients

may request a sleep value for their shared resources in addition to the active

mode requests.

Properties:

- compatible:

	Usage: required

	Value type: <string>

	Definition: Should be "qcom,rpmh-rsc".

- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: The first register specifies the base address of the

		    DRV(s). The number of DRVs in the dependent on the RSC.

	            The tcs-offset specifies the start address of the

	            TCS in the DRVs.

- reg-names:

	Usage: required

	Value type: <string>

	Definition: Maps the register specified in the reg property. Must be

	            "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The

- interrupts:

	Usage: required

	Value type: <prop-encoded-interrupt>

	Definition: The interrupt that trips when a message complete/response

	           is received for this DRV from the accelerators.

- qcom,drv-id:

	Usage: required

	Value type: <u32>

	Definition: The id of the DRV in the RSC block that will be used by

		    this controller.

- qcom,tcs-config:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: The tuple defining the configuration of TCS.

	            Must have 2 cells which describe each TCS type.

	            <type number_of_tcs>.

	            The order of the TCS must match the hardware

	            configuration.

	- Cell #1 (TCS Type): TCS types to be specified -

	            ACTIVE_TCS

	            SLEEP_TCS

	            WAKE_TCS

	            CONTROL_TCS

	- Cell #2 (Number of TCS): <u32>

- label:

	Usage: optional

	Value type: <string>

	Definition: Name for the RSC. The name would be used in trace logs.

Drivers that want to use the RSC to communicate with RPMH must specify their

bindings as child nodes of the RSC controllers they wish to communicate with.

Example 1:

For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the

register offsets for DRV2 start at 0D00, the register calculations are like

this -

DRV0: 0x179C0000

DRV2: 0x179C0000 + 0x10000 = 0x179D0000

DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000

TCS-OFFSET: 0xD00

	apps_rsc: rsc@179c0000 {

		label = "apps_rsc";

		compatible = "qcom,rpmh-rsc";

		reg = <0x179c0000 0x10000>,

		      <0x179d0000 0x10000>,

		      <0x179e0000 0x10000>;

		reg-names = "drv-0", "drv-1", "drv-2";

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

		qcom,tcs-offset = <0xd00>;

		qcom,drv-id = <2>;

		qcom,tcs-config = <ACTIVE_TCS  2>,

				  <SLEEP_TCS   3>,

				  <WAKE_TCS    3>,

				  <CONTROL_TCS 1>;

	};

Example 2:

For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the

register offsets for DRV0 start at 01C00, the register calculations are like

this -

DRV0: 0xAF20000

TCS-OFFSET: 0x1C00

	disp_rsc: rsc@af20000 {

		label = "disp_rsc";

		compatible = "qcom,rpmh-rsc";

		reg = <0xaf20000 0x10000>;

		reg-names = "drv-0";

		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;

		qcom,tcs-offset = <0x1c00>;

		qcom,drv-id = <0>;

		qcom,tcs-config = <ACTIVE_TCS  0>,

				  <SLEEP_TCS   1>,

				  <WAKE_TCS    1>,

				  <CONTROL_TCS 0>;

	};

			reg = <0x740000 0x20000>;

		};

		tsens0: thermal-sensor@4a9000 {

			compatible = "qcom,msm8996-tsens";

			reg = <0x4a9000 0x1000>, /* TM */

			      <0x4a8000 0x1000>; /* SROT */

			#qcom,sensors = <13>;

			#thermal-sensor-cells = <1>;

		};

		tsens1: thermal-sensor@4ad000 {

			compatible = "qcom,msm8996-tsens";

			reg = <0x4ad000 0x1000>, /* TM */

			      <0x4ac000 0x1000>; /* SROT */

			#qcom,sensors = <8>;

			#thermal-sensor-cells = <1>;

		};

		tcsr: syscon@7a0000 {

			compatible = "qcom,tcsr-msm8996", "syscon";

			reg = <0x7a0000 0x18000>;

			status = "disabled";

		};

		tsens0: thermal-sensor@4a8000 {

			compatible = "qcom,msm8996-tsens";

			reg = <0x4a8000 0x2000>;

			#thermal-sensor-cells = <1>;

		};

		blsp2_uart1: serial@75b0000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x75b0000 0x1000>;

			};

		};

		tsens0: thermal-sensor@c263000 {

			compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";

			reg = <0xc263000 0x1ff>, /* TM */

			      <0xc222000 0x1ff>; /* SROT */

			#qcom,sensors = <13>;

			#thermal-sensor-cells = <1>;

		};

		tsens1: thermal-sensor@c265000 {

			compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";

			reg = <0xc265000 0x1ff>, /* TM */

			      <0xc223000 0x1ff>; /* SROT */

			#qcom,sensors = <8>;

			#thermal-sensor-cells = <1>;

		};

		spmi_bus: spmi@c440000 {

			compatible = "qcom,spmi-pmic-arb";

			reg = <0xc440000 0x1100>,

          functions for connecting the underlying serial UART, SPI, and I2C

          devices to the output pins.

config QCOM_LLCC

	tristate "Qualcomm Technologies, Inc. LLCC driver"

	depends on ARCH_QCOM

	help

	  Qualcomm Technologies, Inc. platform specific

	  Last Level Cache Controller(LLCC) driver. This provides interfaces

	  to clients that use the LLCC. Say yes here to enable LLCC slice

	  driver.

config QCOM_SDM845_LLCC

	tristate "Qualcomm Technologies, Inc. SDM845 LLCC driver"

	depends on QCOM_LLCC

	help

	  Say yes here to enable the LLCC driver for SDM845. This provides

	  data required to configure LLCC so that clients can start using the

	  LLCC slices.

config QCOM_MDT_LOADER

	tristate

	select QCOM_SCM

	  Say y here if you intend to boot the modem remoteproc.

config QCOM_RPMH

	bool "Qualcomm RPM-Hardened (RPMH) Communication"

	depends on ARCH_QCOM && ARM64 && OF || COMPILE_TEST

	help

	  Support for communication with the hardened-RPM blocks in

	  Qualcomm Technologies Inc (QTI) SoCs. RPMH communication uses an

	  internal bus to transmit state requests for shared resources. A set

	  of hardware components aggregate requests for these resources and

	  help apply the aggregated state on the resource.

config QCOM_SMEM

	tristate "Qualcomm Shared Memory Manager (SMEM)"

	depends on ARCH_QCOM