Commit afa88bdb authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson into clk-meson 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Fix mpll fractional part and spread sprectrum issues
 - Add meson8 audio clocks
 - Add g12a temperature sensors clocks
 - Add g12a and g12b cpu clocks

* tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: g12a: mark fclk_div3 as critical
  clk: meson: g12a: Add support for G12B CPUB clocks
  dt-bindings: clk: meson: add g12b periph clock controller bindings
  clk: meson-g12a: add temperature sensor clocks
  dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs
  clk: meson: meson8b: add the cts_i958 clock
  clk: meson: meson8b: add the cts_mclk_i958 clocks
  clk: meson: meson8b: add the cts_amclk clocks
  dt-bindings: clock: meson8b: add the audio clocks
  clk: meson: g12a: add controller register init
  clk: meson: eeclk: add init regs
  clk: meson: g12a: add mpll register init sequences
  clk: meson: mpll: add init callback and regs
  clk: meson: axg: spread spectrum is on mpll2
  clk: meson: gxbb: no spread spectrum on mpll0
  clk: meson: mpll: properly handle spread spectrum
  clk: meson: meson8b: fix a typo in the VPU parent names array variable
  clk: meson: fix MPLL 50M binding id typo
parents a188339c eda91833

Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required Properties: 
		"amlogic,gxl-clkc" for GXL and GXM SoC,

		"amlogic,axg-clkc" for AXG SoC.

		"amlogic,g12a-clkc" for G12A SoC.

		"amlogic,g12b-clkc" for G12B SoC.

- clocks : list of clock phandle, one for each entry clock-names.

- clock-names : should contain the following:

  * "xtal": the platform xtal

drivers/clk/meson/axg.c

+5 −5
Original line number Diff line number Diff line
@@ -469,11 +469,6 @@ static struct clk_regmap axg_mpll0_div = { 
			.shift   = 16,

			.width   = 9,

		},

		.ssen = {

			.reg_off = HHI_MPLL_CNTL,

			.shift   = 25,

			.width	 = 1,

		},

		.misc = {

			.reg_off = HHI_PLL_TOP_MISC,

			.shift   = 0,
@@ -568,6 +563,11 @@ static struct clk_regmap axg_mpll2_div = { 
			.shift   = 16,

			.width   = 9,

		},

		.ssen = {

			.reg_off = HHI_MPLL_CNTL,

			.shift   = 25,

			.width	 = 1,

		},

		.misc = {

			.reg_off = HHI_PLL_TOP_MISC,

			.shift   = 2,

drivers/clk/meson/clk-mpll.c

+26 −10
Original line number Diff line number Diff line
@@ -115,21 +115,12 @@ static int mpll_set_rate(struct clk_hw *hw, 
	else

		__acquire(mpll->lock);



	/* Enable and set the fractional part */

	/* Set the fractional part */

	meson_parm_write(clk->map, &mpll->sdm, sdm);

	meson_parm_write(clk->map, &mpll->sdm_en, 1);



	/* Set additional fractional part enable if required */

	if (MESON_PARM_APPLICABLE(&mpll->ssen))

		meson_parm_write(clk->map, &mpll->ssen, 1);



	/* Set the integer divider part */

	meson_parm_write(clk->map, &mpll->n2, n2);



	/* Set the magic misc bit if required */

	if (MESON_PARM_APPLICABLE(&mpll->misc))

		meson_parm_write(clk->map, &mpll->misc, 1);



	if (mpll->lock)

		spin_unlock_irqrestore(mpll->lock, flags);

	else
@@ -138,6 +129,30 @@ static int mpll_set_rate(struct clk_hw *hw, 
	return 0;

}



static void mpll_init(struct clk_hw *hw)

{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);



	if (mpll->init_count)

		regmap_multi_reg_write(clk->map, mpll->init_regs,

				       mpll->init_count);



	/* Enable the fractional part */

	meson_parm_write(clk->map, &mpll->sdm_en, 1);



	/* Set spread spectrum if possible */

	if (MESON_PARM_APPLICABLE(&mpll->ssen)) {

		unsigned int ss =

			mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;

		meson_parm_write(clk->map, &mpll->ssen, ss);

	}



	/* Set the magic misc bit if required */

	if (MESON_PARM_APPLICABLE(&mpll->misc))

		meson_parm_write(clk->map, &mpll->misc, 1);

}



const struct clk_ops meson_clk_mpll_ro_ops = {

	.recalc_rate	= mpll_recalc_rate,

	.round_rate	= mpll_round_rate,
@@ -148,6 +163,7 @@ const struct clk_ops meson_clk_mpll_ops = { 
	.recalc_rate	= mpll_recalc_rate,

	.round_rate	= mpll_round_rate,

	.set_rate	= mpll_set_rate,

	.init		= mpll_init,

};

EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);

drivers/clk/meson/clk-mpll.h

+3 −0
Original line number Diff line number Diff line
@@ -18,11 +18,14 @@ struct meson_clk_mpll_data { 
	struct parm n2;

	struct parm ssen;

	struct parm misc;

	const struct reg_sequence *init_regs;

	unsigned int init_count;

	spinlock_t *lock;

	u8 flags;

};



#define CLK_MESON_MPLL_ROUND_CLOSEST	BIT(0)

#define CLK_MESON_MPLL_SPREAD_SPECTRUM	BIT(1)



extern const struct clk_ops meson_clk_mpll_ro_ops;

extern const struct clk_ops meson_clk_mpll_ops;

drivers/clk/meson/g12a.c

+844 −11

File changed.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE