Commit af68abad authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Fix work handling 



* Currently, there is no synchronization between the reset
  work and the tx-poll work. Fix this and make sure that we
  bail out properly if a reset work is in progress.

* Cleanup the PLL WAR and enable it for AR9340 too and
  use a helper for restarting work/timers after a reset.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent ef1b6cd9

drivers/net/wireless/ath/ath9k/ath9k.h

+1 −0
Original line number Diff line number Diff line
@@ -431,6 +431,7 @@ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); 
#define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */



#define ATH_PAPRD_TIMEOUT	100 /* msecs */

#define ATH_PLL_WORK_INTERVAL   100



void ath_tx_complete_poll_work(struct work_struct *work);

void ath_reset_work(struct work_struct *work);

drivers/net/wireless/ath/ath9k/link.c

+19 −14
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ void ath_tx_complete_poll_work(struct work_struct *work) 
			"tx hung, resetting the chip\n");

		RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);

		ieee80211_queue_work(sc->hw, &sc->hw_reset_work);

		return;

	}



	ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -107,9 +108,9 @@ out: 
}



/*

 * PLL-WAR for AR9485.

 * PLL-WAR for AR9485/AR9340

 */

static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)

static bool ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)

{

	static int count;

	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -117,29 +118,33 @@ static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) 
	if (pll_sqsum >= 0x40000) {

		count++;

		if (count == 3) {

			/* Rx is hung for more than 500ms. Reset it */

			ath_dbg(common, RESET, "Possible RX hang, resetting\n");

			ath_dbg(common, RESET, "PLL WAR, resetting the chip\n");

			RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);

			ieee80211_queue_work(sc->hw, &sc->hw_reset_work);

			count = 0;

			return true;

		}

	} else

	} else {

		count = 0;

	}



	return false;

}



void ath_hw_pll_work(struct work_struct *work)

{

	u32 pll_sqsum;

	struct ath_softc *sc = container_of(work, struct ath_softc,

					    hw_pll_work.work);

	u32 pll_sqsum;



	if (AR_SREV_9485(sc->sc_ah)) {

	ath9k_ps_wakeup(sc);

	pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);

	ath9k_ps_restore(sc);

		ath_hw_pll_rx_hang_check(sc, pll_sqsum);

		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);

	}

	if (ath_hw_pll_rx_hang_check(sc, pll_sqsum))

		return;



	ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,

				     msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));

}



/*

drivers/net/wireless/ath/ath9k/main.c

+17 −5
Original line number Diff line number Diff line
@@ -158,6 +158,22 @@ static void ath_cancel_work(struct ath_softc *sc) 
	cancel_work_sync(&sc->hw_reset_work);

}



static void ath_restart_work(struct ath_softc *sc)

{

	struct ath_common *common = ath9k_hw_common(sc->sc_ah);



	ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);



	if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))

		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,

				     msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));



	ath_start_rx_poll(sc, 3);



	if (!common->disable_ani)

		ath_start_ani(common);

}



static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)

{

	struct ath_hw *ah = sc->sc_ah;
@@ -209,11 +225,7 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start) 
		if (sc->sc_flags & SC_OP_BEACONS)

			ath_set_beacon(sc);



		ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);

		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);

		ath_start_rx_poll(sc, 3);

		if (!common->disable_ani)

			ath_start_ani(common);

		ath_restart_work(sc);

	}



	if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {

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