Commit af655cc5 authored by Thong Thai's avatar Thong Thai Committed by Alex Deucher
Browse files

drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands 



Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.

Signed-off-by: default avatarThong Thai <thong.thai@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9c8c9c7c

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#define AMDGPU_VCN_FIRMWARE_OFFSET	256

#define AMDGPU_VCN_MAX_ENC_RINGS	3



#define VCN_DEC_KMD_CMD 		0x80000000

#define VCN_DEC_CMD_FENCE		0x00000000

#define VCN_DEC_CMD_TRAP		0x00000001

#define VCN_DEC_CMD_WRITE_REG		0x00000004

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+6 −6
Original line number Diff line number Diff line
@@ -1485,7 +1485,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));

}



/**
@@ -1498,7 +1498,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 
static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));

}



/**
@@ -1543,7 +1543,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 
	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);



	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));



	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, 0);
@@ -1553,7 +1553,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 


	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));

}



/**
@@ -1597,7 +1597,7 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 


	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));

}



static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
@@ -1626,7 +1626,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 


	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));

}



/**

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