Commit af63147c authored Feb 04, 2019 by Kan Liang Committed by Ingo Molnar Feb 11, 2019

perf/x86/intel: Add counter freezing quirk for Goldmont



A microcode patch is also needed for Goldmont while counter freezing
feature is enabled. Otherwise, there will be some issues, e.g. PMI lost.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: bp@alien8.de
Link: https://lkml.kernel.org/r/1549319013-4522-5-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Ingo Molnar <mingo@kernel.org>

parent bef9f271

arch/x86/events/intel/core.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -3924,6 +3924,10 @@ static __init void intel_nehalem_quirk(void)
		}

		static const struct x86_cpu_desc counter_freezing_ucodes[] = {
		INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
		INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
		INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
		INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_X, 1, 0x00000028),
		INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
		INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
		{}
		@@ -4295,6 +4299,7 @@ __init int intel_pmu_init(void)

		case INTEL_FAM6_ATOM_GOLDMONT:
		case INTEL_FAM6_ATOM_GOLDMONT_X:
		x86_add_quirk(intel_counter_freezing_quirk);
		memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
		sizeof(hw_cache_event_ids));
		memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,

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