Commit af5fe1e9 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: cleanup GMC v9 TLB invalidation 



Move the kiq handling into amdgpu_virt.c and drop the fallback.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarEmily Deng <Emily.Deng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5c76c6a8

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+40 −0
Original line number Diff line number Diff line
@@ -132,6 +132,46 @@ failed_kiq_write: 
	pr_err("failed to write reg:%x\n", reg);

}



void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,

					uint32_t reg0, uint32_t reg1,

					uint32_t ref, uint32_t mask)

{

	struct amdgpu_kiq *kiq = &adev->gfx.kiq;

	struct amdgpu_ring *ring = &kiq->ring;

	signed long r, cnt = 0;

	unsigned long flags;

	uint32_t seq;



	spin_lock_irqsave(&kiq->ring_lock, flags);

	amdgpu_ring_alloc(ring, 32);

	amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,

					    ref, mask);

	amdgpu_fence_emit_polling(ring, &seq);

	amdgpu_ring_commit(ring);

	spin_unlock_irqrestore(&kiq->ring_lock, flags);



	r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);



	/* don't wait anymore for IRQ context */

	if (r < 1 && in_interrupt())

		goto failed_kiq;



	might_sleep();

	while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {



		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);

		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);

	}



	if (cnt > MAX_KIQ_REG_TRY)

		goto failed_kiq;



	return;



failed_kiq:

	pr_err("failed to write reg %x wait reg %x\n", reg0, reg1);

}



/**

 * amdgpu_virt_request_full_gpu() - request full gpu access

 * @amdgpu:	amdgpu device.

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+3 −0
Original line number Diff line number Diff line
@@ -278,6 +278,9 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 
void amdgpu_virt_init_setting(struct amdgpu_device *adev);

uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);

void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);

void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,

					uint32_t reg0, uint32_t rreg1,

					uint32_t ref, uint32_t mask);

int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);

int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);

int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+6 −47
Original line number Diff line number Diff line
@@ -312,48 +312,6 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 
	return req;

}



static signed long  amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev,

						  uint32_t reg0, uint32_t reg1,

						  uint32_t ref, uint32_t mask)

{

	signed long r, cnt = 0;

	unsigned long flags;

	uint32_t seq;

	struct amdgpu_kiq *kiq = &adev->gfx.kiq;

	struct amdgpu_ring *ring = &kiq->ring;



	spin_lock_irqsave(&kiq->ring_lock, flags);



	amdgpu_ring_alloc(ring, 32);

	amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,

					    ref, mask);

	amdgpu_fence_emit_polling(ring, &seq);

	amdgpu_ring_commit(ring);

	spin_unlock_irqrestore(&kiq->ring_lock, flags);



	r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);



	/* don't wait anymore for IRQ context */

	if (r < 1 && in_interrupt())

		goto failed_kiq;



	might_sleep();



	while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {

		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);

		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);

	}



	if (cnt > MAX_KIQ_REG_TRY)

		goto failed_kiq;



	return 0;



failed_kiq:

	pr_err("failed to invalidate tlb with kiq\n");

	return r;

}



/*

 * GART

 * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -375,7 +333,6 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 
{

	const unsigned eng = 17;

	unsigned i, j;

	int r;



	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {

		struct amdgpu_vmhub *hub = &adev->vmhub[i];
@@ -384,9 +341,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 
		if (adev->gfx.kiq.ring.sched.ready &&

		    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&

		    !adev->in_gpu_reset) {

			r = amdgpu_kiq_reg_write_reg_wait(adev, hub->vm_inv_eng0_req + eng,

				hub->vm_inv_eng0_ack + eng, tmp, 1 << vmid);

			if (!r)

			uint32_t req = hub->vm_inv_eng0_req + eng;

			uint32_t ack = hub->vm_inv_eng0_ack + eng;



			amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,

							   1 << vmid);

			continue;

		}

CRA Git | Maintained and supported by SUSTech CRA and CCSE