Commit af56ff27 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull KVM fixes from Paolo Bonzini:
 "ARM:
   - fixes for ITS init issues, error handling, IRQ leakage, race
     conditions
   - an erratum workaround for timers
   - some removal of misleading use of errors and comments
   - a fix for GICv3 on 32-bit guests

  MIPS:
   - fix for where the guest could wrongly map the first page of
     physical memory

  x86:
   - nested virtualization fixes"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  MIPS: KVM: Check for pfn noslot case
  kvm: nVMX: fix nested tsc scaling
  KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write
  KVM: nVMX: fix msr bitmaps to prevent L2 from accessing L0 x2APIC
  arm64: KVM: report configured SRE value to 32-bit world
  arm64: KVM: remove misleading comment on pmu status
  KVM: arm/arm64: timer: Workaround misconfigured timer interrupt
  arm64: Document workaround for Cortex-A72 erratum #853709
  KVM: arm/arm64: Change misleading use of is_error_pfn
  KVM: arm64: ITS: avoid re-mapping LPIs
  KVM: arm64: check for ITS device on MSI injection
  KVM: arm64: ITS: move ITS registration into first VCPU run
  KVM: arm64: vgic-its: Make updates to propbaser/pendbaser atomic
  KVM: arm64: vgic-its: Plug race in vgic_put_irq
  KVM: arm64: vgic-its: Handle errors from vgic_add_lpi
  KVM: arm64: ITS: return 1 on successful MSI injection
parents 5e608a02 ba913e4f

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ stable kernels. 
| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    |

| ARM            | Cortex-A57      | #852523         | N/A                     |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220    |

| ARM            | Cortex-A72      | #853709         | N/A                     |

| ARM            | MMU-500         | #841119,#826419 | N/A                     |

|                |                 |                 |                         |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |

arch/arm/kvm/mmu.c

+1 −1
Original line number Diff line number Diff line
@@ -1309,7 +1309,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 
	smp_rmb();



	pfn = gfn_to_pfn_prot(kvm, gfn, write_fault, &writable);

	if (is_error_pfn(pfn))

	if (is_error_noslot_pfn(pfn))

		return -EFAULT;



	if (kvm_is_device_pfn(pfn)) {

arch/arm64/kvm/hyp/switch.c

+1 −1
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ static int __hyp_text __guest_run(struct kvm_vcpu *vcpu) 


	/*

	 * We must restore the 32-bit state before the sysregs, thanks

	 * to Cortex-A57 erratum #852523.

	 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).

	 */

	__sysreg32_restore_state(vcpu);

	__sysreg_restore_guest_state(guest_ctxt);

arch/arm64/kvm/sys_regs.c

+1 −9
Original line number Diff line number Diff line
@@ -823,14 +823,6 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
 * Architected system registers.

 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2

 *

 * We could trap ID_DFR0 and tell the guest we don't support performance

 * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was

 * NAKed, so it will read the PMCR anyway.

 *

 * Therefore we tell the guest we have 0 counters.  Unfortunately, we

 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for

 * all PM registers, which doesn't crash the guest kernel at least.

 *

 * Debug handling: We do trap most, if not all debug related system

 * registers. The implementation is good enough to ensure that a guest

 * can use these with minimal performance degradation. The drawback is
@@ -1360,7 +1352,7 @@ static const struct sys_reg_desc cp15_regs[] = { 
	{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },



	/* ICC_SRE */

	{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },

	{ Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },



	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },

arch/mips/kvm/mmu.c

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static int kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) 
	srcu_idx = srcu_read_lock(&kvm->srcu);

	pfn = gfn_to_pfn(kvm, gfn);



	if (is_error_pfn(pfn)) {

	if (is_error_noslot_pfn(pfn)) {

		kvm_err("Couldn't get pfn for gfn %#llx!\n", gfn);

		err = -EFAULT;

		goto out;

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