Commit af4e1c5e authored by Marcel Bocu's avatar Marcel Bocu Committed by Guenter Roeck
Browse files

x86/amd_nb: Add PCI device IDs for family 17h, model 70h 



The AMD Ryzen gen 3 processors came with a different PCI IDs for the
function 3 & 4 which are used to access the SMN interface. The root
PCI address however remained at the same address as the model 30h.

Adding the F3/F4 PCI IDs respectively to the misc and link ids appear
to be sufficient for k10temp, so let's add them and follow up on the
patch if other functions need more tweaking.

Vicki Pfau sent an identical patch after I checked that no-one had
written this patch. I would have been happy about dropping my patch but
unlike for his patch series, I had already Cc:ed the x86 people and
they already reviewed the changes. Since Vicki has not answered to
any email after his initial series, let's assume she is on vacation
and let's avoid duplication of reviews from the maintainers and merge
my series. To acknowledge Vicki's anteriority, I added her S-o-b to
the patch.

v2, suggested by Guenter Roeck and Brian Woods:
 - rename from 71h to 70h

Signed-off-by: default avatarVicki Pfau <vi@endrift.com>
Signed-off-by: default avatarMarcel Bocu <marcel.p.bocu@gmail.com>
Tested-by: default avatarMarcel Bocu <marcel.p.bocu@gmail.com>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarBrian Woods <brian.woods@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# pci_ids.h

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Cc: "Woods, Brian" <Brian.Woods@amd.com>
Cc: Clemens Ladisch <clemens@ladisch.de>
Cc: Jean Delvare <jdelvare@suse.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: linux-hwmon@vger.kernel.org
Link: https://lore.kernel.org/r/20190722174510.2179-1-marcel.p.bocu@gmail.com


Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
parent 899df7b4

arch/x86/kernel/amd_nb.c

+3 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define PCI_DEVICE_ID_AMD_17H_DF_F4	0x1464

#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec

#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494

#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444



/* Protect the PCI config register pairs used for SMN and DF indirect access. */

static DEFINE_MUTEX(smn_mutex);
@@ -50,6 +51,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { 
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },

	{}

};

EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
@@ -63,6 +65,7 @@ static const struct pci_device_id amd_nb_link_ids[] = { 
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },

	{}

};

include/linux/pci_ids.h

+1 −0
Original line number Diff line number Diff line
@@ -548,6 +548,7 @@ 
#define PCI_DEVICE_ID_AMD_17H_DF_F3	0x1463

#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb

#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493

#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443

#define PCI_DEVICE_ID_AMD_CNB17H_F3	0x1703

#define PCI_DEVICE_ID_AMD_LANCE		0x2000

#define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001

CRA Git | Maintained and supported by SUSTech CRA and CCSE