Commit af231172 authored by Kevin Cernekee's avatar Kevin Cernekee Committed by Ralf Baechle
Browse files

MIPS: Add BMIPS CP0 register definitions 



Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: default avatarFlorian Fainelli <ffainelli@freebox.fr>
Patchwork: https://patchwork.linux-mips.org/patch/1708/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c1c0c461

arch/mips/include/asm/mipsregs.h

+51 −0
Original line number Diff line number Diff line
@@ -1040,6 +1040,12 @@ do { \ 
#define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)

#define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)



#define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)

#define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)



#define read_c0_staglo()	__read_32bit_c0_register($28, 4)

#define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)



#define read_c0_taghi()		__read_32bit_c0_register($29, 0)

#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
@@ -1082,6 +1088,51 @@ do { \ 
#define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)

#define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)



/* BMIPS3300 */

#define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)

#define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)



#define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)

#define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)



#define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)

#define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)



/* BMIPS4380 */

#define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)

#define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)



#define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)

#define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)



#define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)

#define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)



#define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)

#define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)



#define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)

#define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)



/* BMIPS5000 */

#define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)

#define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)



#define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)

#define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)



#define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)

#define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)



#define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)

#define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)



#define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)

#define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)



#define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)

#define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)



/*

 * Macros to access the floating point coprocessor control registers

 */

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